International Business Machines Corporation

Raymond J Pedersen

Stephen J Nadas

Viktors Berstis

Bradly George Frey

Arnold Weinberger

Ronald F Hill

Robert J Bullions, Iii

John A Kiselak, Ii

Lance H Johnson

Edward A Nadarzynski

Louis R Bryant

A first-in-first-out queue is used to manage instruction sequence execution from an instruction cache in a computer processor. Fields are provided in the queue element structure for not only referencing the correct instruction cache line but also for specifying cache line subsequences and the location of branch instructions so as to cause subsequent execution from other cache lines. The structure is particularly supportive of instruction loops and provides significant performance improvement through the elimination of unnecessary cache line writeovers.

Instruction cache access and prefetch process controlled by a predicted

A hardware controlled pipelined processor having an interpretive storage and multiple execution units employs interpretive storage 'milli-instructions' and an interpretive execution 'milli-mode'. Additional hardware controlled instructions that are exclusively used in milli-mode may be added to provide additional controls or to improve performance (they augment the architected instruction set). Milli-mode routines intermingle milli-mode only instructions with architected instructions to implement complex functions. One milli-instruction called the DRAIN INSTRUCTION PIPELINE (DIP) causes the pipeline to drain selectively so the milli-programmer determines when and and what type of pipeline drain to perform. A DRAIN INSTRUCTION PIPELINE causes suspension of decoding until a selected event occurs. This DIP instruction includes options for suspending decoding until one of the following events have occurred: 1. all conceptually previous macro-instructions have completed; 2. all conceptually previous instructions have completed; 3. all store requests have reached the point where no exceptions would occur, but the actual store may not have completed; 4. all conceptually previous stores from all conceptually previous units-of-operation have competed (serialize); or 5. invalidate instruction buffers and fetch the next sequential macro-instructions.

Computer system permitting switching between architected and

An alternate instruction architecture which uses the preexisting dataflow and hardware controlled execution units of an otherwise conventional pipelined processor to accomplish complex functions. Additional hardware controlled instructions (private milli-mode only instructions) are added to provide control functions or to improve performance. These milli-mode instructions augment the standard 'user visible' architected instruction set (which in the preferred embodiment is the System 390 instruction set). Millicode routines can intermingle the milli-mode only instructions with standard system instructions to implement complex functions. The set of instructions available in milli-mode can be considered to be an alternate architecture that the processor can execute. The millicode and standard system architectures each have there own set of architected registers. However, these registers are dynamically taken from and returned to a common physical register pool under control of a register management system. Provision is also made for communication between the two architectures such that data in the milli-registers and the standard architected registers (such as GPRs) can be exchanged. A set of register operand registers is provided to enable explicit updates of general purpose registers from millicoded routines. Both milli-instructions and standard architecture instructions can be present in the pipeline simultaneously. Provision is thus also made for performing a controlled pipeline reset of the facilities manipulated by the two types of architectures.

Millicode register management and pipeline reset

The disclosure describes means for allowing the sequencing of operand fetches to deviate from the conceptual sequence specified in the program. Allowing fetch sequencing deviations may improve system performance, while not causing any deviation in program execution results. Out-of-sequence (OOS) fetching may be caused by issuing each fetch without regard to the following conditions: 1. a delay in issuance to storage (such as a delay in generating the address for a fetch request); 2. a speed up in operand data return (such as due to fetching the operand data from a store buffer in the execution unit without going to storage for the data); 3. a delay in the return of operand data (such as when a fetch request has a cache miss and its data must be obtained from the storage hierarchy); or 4. an overlap in the return of fetch data for a serializer instruction with execution of instructions preceding the serializer or data and instruction fetching for instructions following the serializer before its completion. Each fetch operand of a serializer is handled as OOS even when it is not OOS in order to eliminate serialized fetching. Operand store compare (OSC) controls are provided to control an OOS fetch dependent on a conceptually prior store operand. If an OOS condition is detected that possibly may have caused wrong data, an execution retry occurs beginning with the currently incomplete instruction stream, and the retry may include OOS fetching. The integrity of data is maintained when an OOS fetch operand is exposed to a cross-invalidation (XI) hit by the storage request of another CPU in a multiprocessor (MP) system.

Coordination of out-of-sequence fetching between multiple processors

A binary number substitution mechanism includes first and second storage arrays addressed by first and second portions, respectively, of an input binary number, producing a substitute output binary number. The input binary number represents a predetermined number of microinstruction addresses in a read-only store, and the output binary number is representative of microinstruction addresses in a main storage device. Only a limited number of the possible input binary numbers are required to access the first and second storage arrays to read out selectively stored binary numbers to create a limited range of output binary numbers unique to each of the limited number of the input binary numbers.

Binary number substitution mechanism in a control store element

A microinstruction control storage mechanism includes a read-only store (ROS), writeable control store (WCS), first cycle control store, and a reserved portion of main storage in a data processing system. The ROS stores frequently used sequences of microinstructions and is not altered during operation. Other sequences of microinstructions which are not frequently used are stored in the reserved portion of main storage. As required, blocks of microinstructions are paged into the WCS from the main storage. One cycle of execution is saved for each machine instruction by utilizing the operation code portion directly from the instruction register of the data processing system to access a microinstruction from the first cycle control store. An array of single-bit storage devices, accessed by microinstruction addresses also utilized to access microinstructions from the ROS, signal the existence of a faulty microinstruction from the ROS as determined by maintenance or design personnel. In response to a halt signal from an accessed single-bit storage device, an address substitution mechanism creates a microinstruction address which identifies a main storage location and may have to be used to initiate transfer of a block of microinstructions from main storage to the WCS to provide access to a particular substitute microinstruction for the faulty microinstruction.

Microinstruction substitution mechanism in a control store

A digital LRU network in which a use value in a chronology register always appears to be increasing; it is incremented for each access to a different data block currently represented in an active LRU array and this use value is copied into an index for that block in an active use-value array. Special circuits are provided to maintain the appearance of continuously increasing use values. At the start of each array search, the special circuits check the chronology register to determine if its use value is nearing its highest registerable value by testing its two high order bits for 1's. If so, the chronology register is set to 100...0, which is higher than any use value in the active array, after the use values in the active array are shifted one bit position to the right by writing them into corresponding positions in another array, which then becomes the active array. The right shift drops the low-order bit in the use values and sets the high-order bit to zero. The right shift increases the range of use values that can subsequently be set into the active array without affecting the stored relationships among the existing use values, and enables the incrementing of use values to continue. The second array is used to permit overlap of the read cycle of one array with the write cycle of the other array.

Growing community of inventors

Boca Raton, FL, United States of America

Raymond J Pedersen