International Business Machines Corporation

Raymond J Ferreri

Steven Magdo

Glenn E Holmes

Walter R Heitmueller

Douglas B Fields

An automated, custom personalization process for generating integrated gate array chips is defined which enhances yield and reliability potential. Unused data provided in the general purpose design is deleted through a selective detection procedure based on circuit utilization.

Method of integrated circuit chips design

A method, for producing a multi-layer metallization pattern (macro) for a custom sized memory embedded on a masterslice, is disclosed. The memory has 'n' addresses and stores 'm' bits at each address. Specifically, the memory relies on using macros for a 'seed' portion and a 'stitch' portion of the memory. The seed portion is a small complete memory. The seed contains all the ancillary support circuitry, e.g. address decoders and true/complement generators, used by the entire embedded memory and a small amount of memory locations, typically having 'n' rows each one or two bits wide, with their associated data transfer circuits. A 'stitch' is one column of 'n' memory locations and the data transfer circuits required to serve these locations. Once the macro for the seed is appropriately positioned on the masterslice, then the stitch macro is replicated as many times as needed in contiguous columns outwardly spaced from and vertically aligned with the seed in order to provide the desired number of bits ('m') in each row of the embedded memory. Vertically aligning all the stitches with the seed ensures that corresponding rowlines located within the seed and in each stitch are joined together.

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Stormville, NY, United States of America

Raymond J Ferreri