International Business Machines Corporation

Raymond J Bulaga

Donald Lawrence Wheater

John L Harris

Anne Elizabeth Gattiker

Mark Steven Styduhar

Phillip J Nigh

Jody John Van Horn

Douglas R Firth

Leo A Noel

Brooks A Cummings

William J Thibault

John K Masi

Christina L Newman

Patrick W Miller

A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

Method for test optimization using historical and actual fabrication test data

An integrated test structure adapted to facilitate manufacturing verification of microelectronic devices such as Digital to Analog Converters (DAC) is disclosed. The test circuitry and the Circuit Under Test (CUT) are placed on an IC along with an arbitrary amount of digital logic, which drives the input of the CUT. These inputs are translated into an analog output. During a manufacturing test, this output is measured in order to determine that the IC has been manufactured correctly. The analog input of the circuit is coupled to the analog output of the DAC. The digital output of the test circuitry is coupled to the digital logic on the IC. This configuration comprises a Built In Self Test (BIST) structure. The invention allows BIST by eliminating the need to measure the analog output of the DAC external to the IC, and enables testing the CUT by using standard digital BIST techniques.

Integrated test structure and method for verification of microelectronic devices

A method and structure for testing an A to D converter containing a plurality of discrete components is provided. The testing methodology includes dividing the circuit into a number of segments of the discrete components (for testing purposes only) with each segment having the same number of discrete components or an unequal but known number of discrete components. The value of the components individually and collectively of each segment is tested and compared with the value of the corresponding components of at least one other segment, and an output signal is generated of the compared value of the segments being tested. Preferably, the components are in a ladder configuration and are either resistors or capacitors. The testing of the components takes place by impressing constant voltage reference signal to at least a portion of one of the segments, sampling and holding this value and then providing a similar reference signal to complementary components of the other of said segments being compared, and comparing the output signal from each of the segments.

Built in self test method and structure for analog to digital converter

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Richmond, VT, United States of America

Raymond J Bulaga