Applied Materials, Inc.

University of California

Raymond Hoiman Hung

Kenneth S Collins

Avgerinos V Gelatos

Michael Robert Rice

David Walter Groechel

Gerald Z Yin

Douglas Buchberger

John R Trow

Joshua Chiu-Wing Tsui

Joseph P Caulfield

Eric Askarinam

Mei Yin Chang

Bo Zheng

Tae Hong Ha

Jian Ding

Wei Lei

Anshul Vyas

Srinivas D Nemani

Ellie Y Yieh

Xianmin Tang

Yu Lei

Andrew C Kummel

Hongching Shan

Yi Xu

Ruiping Wang

Takashi Kuratomi

Xuesong Lu

Mark Hyun Lee

Jong Choi

Christopher Ahles

Namsung Kim

Ru-Liang Julian Lee

Szuheng Ho

Mehul B Naik

Christopher Dennis Bencher

Schubert S Chu

Errol Antonio C Sanchez

He Ren

Gaurav Thareja

Huixiong Dai

Hui W Chen

Patricia M Liu

Kai Wu

Xuebin Li

Kazuya Daito

Shiyu Sun

David T Or

Hongqing Shan

Vikash Banthia

Tatsuya E Sato

Bingxi Sun Wood

Michael G Haverty

Michael Duane

Xi Cen

Jeremiah T Pender

Yongmei Chen

Shirish A Pethe

Jen Shu

Guoqiang Jian

Nam Sung Kim

Chi-Chou Lin

Jon Mohn

Jing Zhou

Feiyue Ma

Chunshi Cui

Jenn-Yue Wang

Chih-Yang Chang

Chorng-Ping Chang

Henry Fong

Susie Xiuru Yang

Christopher Siu Wing Ngai

Yiming Lai

Jia Ye

Thomas Joseph Kropewnicki

Yakuan Yao

Xumou Xu

Kenneth MacWilliams

Charles Peter Auglis

John Mohn

Jiahua Yu

Methods for producing a reduced contact resistance for cobalt-titanium structures. In some embodiments, a method comprises depositing a titanium layer using a chemical vapor deposition (CVD) process, depositing a first cobalt layer on the titanium nitride layer using a physical vapor deposition (PVD) process, and depositing a second cobalt layer on the first cobalt layer using a CVD process.

Methods for controlling contact resistance in cobalt-titanium structures

Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide. In some embodiments, a method may comprise selectively depositing a metal silicide layer on an Epi surface and adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function for a P type Epi surface may be adjusted to a value of approximately 5.0 eV and the work function for an N type Epi surface may be adjusted to a value of approximately 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to deposition of a contact etch stop layer and an activation anneal.

Integrated contact silicide with tunable work functions

Methods and apparatus for producing a reduced contact resistance for cobalt-titanium structures. In some embodiments, a method comprises depositing a titanium layer using a chemical vapor deposition (CVD) process, depositing a titanium nitride layer on the titanium layer using an atomic layer deposition (ALD) process, depositing a first cobalt layer on the titanium nitride layer using a physical vapor deposition (PVD) process, and depositing a second cobalt layer on the first cobalt layer using a CVD process.

Methods and apparatus for controlling contact resistance in cobalt-titanium structures

Methods and apparatus for selectively depositing a tungsten layer atop a dielectric surface. In embodiments the method includes: depositing a tungsten layer via a physical vapor deposition (PVD) process atop a substrate field and atop a sidewall and a dielectric bottom surface of a feature disposed in a substrate to form a first tungsten portion having a first thickness atop the substrate field, a second tungsten portion having a second thickness atop the sidewall, and a third tungsten portion having a third thickness atop the dielectric bottom surface, wherein the second thickness is less than the first thickness and third thickness; oxidizing a top surface of the tungsten layer to form a first oxidized tungsten portion atop the substrate field, a second oxidized tungsten portion atop the side wall, and a third oxidized tungsten portion atop the dielectric bottom surface; removing the first oxidized tungsten portion, the second oxidized tungsten portion and the third oxidized tungsten portion, wherein the second tungsten portion is completely removed from the sidewall; and passivating or completely removing the first tungsten portion from the substrate field.

Methods for selective deposition of tungsten atop a dielectric layer for bottom up gapfill

The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.

Method for forming a metal gapfill

The systems and methods discussed herein are for a cluster tool that can be used for MOSFET device fabrication, including NMOS and PMOS devices. The cluster tool includes process chambers for pre-cleaning, metal-silicide or metal-germanide film formation, and surface protection operations such as capping and nitridation. The cluster tool can include one or more process chambers configured to form a source and a drain. The devices fabricated in the cluster tool are fabricated to have at least one protective layer formed over the metal-silicide or metal-germanide film to protect the film from contamination during handling and transfer to separate systems.

In-situ integrated chambers

The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.

Pre-clean of silicon germanium for pre-metal contact at source and drain and pre-high K at channel

Embodiments of the disclosure relate to selective metal silicide deposition methods. In one embodiment, a substrate having a silicon containing surface is heated and the silicon containing surface is hydrogen terminated. The substrate is exposed to sequential cycles of a MoFprecursor and a SiHprecursor which is followed by an additional SiHoverdose exposure to selectively deposit a MoSimaterial comprising MoSion the silicon containing surface of the substrate. Methods described herein also provide for selective native oxide removal which enables removal of native oxide material without etching bulk oxide materials.

Selective deposition of metal silicides

Embodiments of the disclosure relate to selective metal silicide deposition methods. In one embodiment, a substrate having a silicon containing surface is heated and the silicon containing surface is hydrogen terminated. The substrate is exposed to sequential cycles of a MoFprecursor and a SiHprecursor which is followed by an additional SiHoverdose exposure to selectively deposit a MoSimaterial comprising MoSion the silicon containing surface of the substrate.

Pre-clean of silicon germanium for pre-metal contact at source and drain and pre-high k at channel

Embodiments disclosed herein relate to an improved transistor with reduced parasitic capacitance. In one embodiment, the transistor device includes a three-dimensional fin structure protruding from a surface of a substrate, the three-dimensional fin structure comprising a top surface and two opposing sidewalls, a first insulating layer formed on the two opposing sidewalls of the three-dimension fin structure, a sacrificial spacer layer conformally formed on the first insulating layer, wherein the sacrificial spacer layer comprises an aluminum oxide based material or a titanium nitride based material, and a second insulating layer conformally formed on the sacrificial spacer layer.

Method of fabricating air-gap spacer for N7/N5 finFET and beyond

Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.

Double exposure patterning with carbonaceous hardmask

A plasma reactor for processing a workpiece includes a reactor enclosure defining a processing chamber, a base within the chamber for supporting the workpiece during processing thereof, a semiconductor window electrode overlying the base, a gas inlet system for admitting a plasma precursor gas into the chamber, an electrical terminal coupled to the semiconductor window electrode, an inductive antenna adjacent one side of the semiconductor window electrode opposite the base for coupling power into the interior of said chamber through the semiconductor window electrode.

Plasma reactor having an inductive antenna coupling power through a parallel plate electrode

An oxide etching process, particular useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. The invention preferably uses the unsaturated 4-carbon fluorocarbons, specifically hexafluorobutadiene (C F ), which has a below 10&deg;C. and is commercially available. The hexafluorobutadiene together with argon is excited into a high-density plasma in a reactor which inductively couples plasma source power into the chamber and RF biases the pedestal electrode supporting the wafer. Preferably, a two-step etch is used process is used in which the above etching gas is used in the main step to provide a good vertical profile and a more strongly polymerizing fluorocarbon such as difluoromethane (CH F ) is added in the over etch to protect the nitride corner.

Highly selective oxide etch process using hexafluorobutadiene

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Cupertino, CA, United States of America

Raymond Hoiman Hung