Tektronix, Inc.

Raymond Hayes

Joseph R Peter

Kei-Wean Calvin Yang

Denis L Heidtmann

John E Taggart

A serial-parallel-serial, charged-coupled device includes an array of horizontal rows and columns of closely spaced charge storage cells. Each storage cell is formed by an electrode covering an insulation layer above a semiconductor substrate. The semiconductor substrate of each storage cell includes a channel region for conducting carriers laterally through the storage cell. The channel region of each storage cell included both in a first row of the array and in any column of the array has a tilted potential gradient providing an electric field facilitating charge carrier drift within the channel region in two lateral directions, toward a neighboring storage cell of the first row and also toward a neighboring storage cell of its column.

Tilted channel, serial-parallel-serial, charge-coupled device

A two phase shift register comprises four serial registers each having an input section, a transfer section, and a lead-in section disposed between the input section and the transfer section. The input sections provide respective sequences of charge samples, the four sequences being offset in phase relative to each other by 90.degree. within the cycle of a clock signal. At least one of the serial registers comprises a first lead-in gate pair and a second lead-in gate pair over the lead-in section, the second lead-in gate pair being between the first lead-in gate pair and the transfer section. The first lead-in gate pair and the second lead-in gate pair are each driven at the frequency of the clock signal, the drive signal applied to the second lead-in gate pair being retarded in phase relative to that applied to the first lead-in gate pair by 90.degree. within the cycle of the clock signal.

Charge-coupled device shift register

A CCD is fabricated from an intermediate product comprising a body of semiconductor material having a channel region of a first conductivity type bounded by a substrate region of a second, opposite conductivity type and a surface of the body, and first and second gates overlying the surface and spaced from each other. The method comprises introducing a dopant into the channel region by way of the surface of the body. The first and second gates are opaque with respect to the dopant. The dopant is such that it forms a zone within the channel region, beneath the space between the first and second gates, and the zone is of the first conductivity type and is of a higher doping concentration than other portions of the channel region. A third gate is formed over the surface of the body of semiconductor material, the third gate being at least partially disposed across the space between the first and second gates.

Electrode structure for a corner turn in a series-parallel-series charge

A charge coupled device (CCD) analog shift register in a two-channel serial-parallel-serial (SPS) structure operating in a fast-in/slow-out (FISO) mode for high speed signal acquisition and temporary storage of a plurality of samples. The two CCD arrays are clocked simultaneously, and the input analog signal is demultiplexed to the two arrays. Additional transfer electrodes are provided at the input of one of the arrays, and the other array is provided with a sampling clock which is 180.degree. out of phase with the sampling clock of the first array; two consecutive samples of the input signal are taken during each transfer clock cycle. All signal samples are clocked through the arrays simultaneously and appear at the output at the same time.

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Beaverton, OR, United States of America

Raymond Hayes