Qualcomm Incorporated

International Business Machines Corporation

Advanced Micro Devices Corporation

Raymond George Stephany

Kern Rim

Xiangdong Chen

Stanley Seungchul Song

Ohsang Kwon

Choh Fei Yeap

John Jianhong Zhu

Foua Vang

Haining S Yang

Mark W Michael

Zhongze Wang

Esin Terzioglu

Hyeokjin Lim

Eric Bernard Schorn

Mukul Gupta

Mickael Malabry

Jingwei Zhang

Hyeokjin Bruce Lim

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

Hybrid coloring methodology for multi-pattern technology

A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

Variable interconnect pitch for improved performance

A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

Grounding dummy gate in scaled layout design

The present invention is directed to a contact resistance test structure and methods of using same. In one illustrative embodiment, the method includes forming a test structure comprised of two gate electrode structures, forming a plurality of conductive contacts to a doped region between the two gate electrode structures, forcing a current through the test structure and determining a resistance of at least one of the conductive contacts based upon, in part, the forced current.

Contact resistance test structure and methods of using same

A high performance dynamic logic compatible transparent latch is provided. The latch comprises a first switchable invertor circuit, a second invertor circuit, and a third switchable invertor circuit. The first invertor, having a data input, a clock input and an output, is enabled by a first phase of an input clock and is disabled by a second phase of the input clock. The second invertor has an input connected to the first invertor output. The third invertor has a clock input, and is enabled by the second phase of the input clock and disabled by the first phase of the input clock, and further has an input connected to the second invertor output and an output connected to the second invertor input.

High performance dynamic logic compatible and scannable transparent latch

Growing community of inventors

Austin, TX, United States of America

Raymond George Stephany