International Business Machines Corporation

S&c Electric Company

Raymond E Losinger

Joseph P Buonomo

Eric M Foster

Chuck Hong Ngai

Dennis E Franklin

Wai Man Lam

James W Valashinas

Steven R Houghtalen

Daniel James Sucher

Burton L Oliver

Sivarama K Kodukula

Palmer W Agnew

Anne S Kellerman

Lauren Lee Post

Robert William Callahan

John J Erhard

Harry L Tredennick

Brion N Shimamoto

Copy protection is provided at a mass storage device provided in or connected to a decoder for receiving digital transmissions of audio and video program material by virtual scrambling of blocks of data. Non-sequential storage locations for blocks of data are defined in accordance with a key and the file allocation table is encrypted and stored. Thus blocks of data remain intact and need not be decrypted upon playback, reducing processing time, while the program is effectively protected from reassembly without decryption of the file allocation table. The key(s) may be maintained internally within the decoder and need not be shared, thus avoiding a need for user identification and/or authentication. Software for encryption, including keys may be downloaded to the decoder through the same transmission link used for transmission of data files that may be encrypted in response to control signals or flags transmitted with data files to be protected.

File table copy protection for a storage device when storing streaming content

Two data streams derived from a transmitted data stream are remultiplexed with a coarser granularity for storage in data blocks which assure that corresponding portions of each of the two data streams are made available in the same data block. The data streams are buffered in queues from which sub-blocks are transferred as buffer sections having sizes corresponding to relative bit rates therein in the order the sub-blocks are filled, preferably using bytes to interrupt processing. Thus, the sub-blocks will be grouped into data blocks in accordance with the correspondence of the data streams such as the time correspondence of audio and video data. As applied to digital video data transmissions, a system time clock (STC) value is stored in a sub-block header and/or a data block header and, using a look-up table or other arrangement for estimating a storage location, a data block can be retrieved from storage in accordance with a target STC value.

Remultiplexing audio/video PES streams from an MPEG transport system

Data corrupted or lost in transmission over a lossy digital transmission link is replaced and/or omitted from data presented in connection with storage to and read out from a mass storage device. Different procedures are used to conceal artifacts corresponding to errored data based upon valid data preceding and following the error in a data stream and a size of the error.

Processing errors in MPEG data as it is sent to a fixed storage device

A method and apparatus for processing a transport stream. A transport stream is received in a data processing system in which the transport stream contains data packets. These data packets include audio data and video data. Data from the data packets in the transport stream are placed into a data packet having a selected size. The selected size of the data packet is limited using a threshold and data from the transport stream, wherein the selected sized of the data packet is optimized for processing within the data processing system.

Method and apparatus for coalescing and packetizing data

A computer system has a universal channel and control unit to interface, with a minimum complexity, to a plurality of different I/O adapters such as a Token Ring adapter or an Ethernet adapter. The system comprises a main processor with main memory, an I/O processor coupled to the main processor by a bus, and a channel program which runs on the I/O processor. The channel program accesses the processor and main memory. The channel program and main processor communicate with a first I/O program protocol. A control unit program also runs on the I/O processor and interfaces the channel program to a plurality of different I/O adapters with a second relatively simple, universal I/O program protocol. Each of the I/O adapters also has a different I/O program protocol than the other I/O adapters and the first I/O protocol, for communication with their respective device.

Channel and control unit having a first I/O program protocol for

A microprocessor chip which is capable of executing a specific subset of instructions on behalf of the main storage portion of a computer memory can be made to emulate direct execution instructions not in that specific subset while working on behalf a control storage portion of the computer memory in a manner which is transparent to the main storage portion by means of a novel set of operand space selection instructions in the control storage portion and a novel switching circuit on the microprocessor chip which controls the access of the chip to the control store portion and the main store portion.

Microprocessor implemented data processing system capable of emulating

A multi-microprocessor implemented data processing system having a single cycle data transfer capability for its memory mapped peripheral devices is described. A host or controlling microprocessor provides address and control signals for memory accesses. In addition, it also determines that a peripheral operation is desired. When this occurs, a command is sent to the selected peripheral and a memory cycle, fetch or store, for the data transfer is initiated. The address bus is provided with the memory address for the needed data and a special decode that indicates the unique nature of this memory access. Logic circuit means are provided to detect the special decode and to intercept the data bus at the appropriate point in the bus cycle in response thereto. The logic circuit means is adapted to then responsively apply the correct control signals to the peripheral to enable the desired data transfer after the data bus has been intercepted.

Apparatus and method for direct memory to peripheral and peripheral to

Synchronization of peripheral operation with that of a processor in a multi-microprocessor implemented data processing system is achieved by bus cycle alteration. A logic circuit is provided for monitoring the condition of a peripheral's status bits and for preventing an appropriate processor control signal from completing the present bus cycle if the peripheral of interest is not able to accept an access. The peripheral of interest is readily identified by providing unique memory mapped locations, one for each system peripheral, that are responsively connected to the logic circuit.

Apparatus and method for synchronization of peripheral devices via bus

The performance of a multimicroprocessor implemented data processing system that emulates a mainframe is enhanced by providing a pair of override latches that serve to steer accesses between main and control storage for instruction fetch and operand acquisition in a manner that minimizes the complexity and size of microprocessor interface microcoding. This is achieved by connecting the instruction and operand override latches between a primary microprocessor, a secondary microprocessor, off-chip control storage belonging to the secondary microprocessor, particularly memory mapped private storage therein, and main storage. The override latches are made responsive, via microcode provided for that purpose, to the type and cause of each memory access. The override latches are set or reset by a memory mapped write to a predefined address in the secondary control store after being enabled by control lines responsive to the particular microprocessor action being taken. When set, the instruction override latch directs all expected primary processor main storage instruction fetches to control store. When set, the operand override latch directs all expected primary processor main storage operand accesses to control store. As appropriate for instruction execution, either one or both of the primary or secondary microprocessors can thereby be transparently latched to main or control storage.

Storage selection override apparatus for a multimicroprocessor

Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. A mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip. The application of this method requires partitioning that makes each identified high performance subset executable on one microprocessor in the current state of technology, a way to quickly pass control back and forth between all of the microprocessors, a suitable way to pass data back and forth between all of the microprocessors, and a technology in which it is economically feasible to have several copies of a complex data flow and control store mechanism.

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Endicott, NY, United States of America

Raymond E Losinger