Intel Corporation

Tahoe Research, Ltd.

Raymond E Cotner

Lawrence N Brigham

Robert S Chau

Walid M Hafez

Chia-Hong Jan

Joodong Park

Makarem A Hussein

Gopinath Bhimarasetti

Weimin Han

Yung-Huei Lee

Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same

A transistor comprising a deposited dual-layer spacer structure and method of fabrication. A polysilicon layer is deposited over a gate dielectric, and is subsequently etched to form the polysilicon gate electrode of the transistor. Next, oxide is deposited over the surface of the gate electrode, followed by deposition of a second dielectric layer. Spacers are then formed adjacent to the gate electrode by etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the oxide.

Transistor having a deposited dual-layer spacer structure

An insulating layer in a semiconductor device and a process for forming the insulating layer is described. The insulating layer comprises of a nitride layer over the substrate having a residual stress of between -8.times.10.sup.9 dynes/cm.sup.-2 and -3.times.10.sup.10 dynes/cm.sup.-2. The insulating layer can further comprise a doped oxide layer under the nitride layer and can further comprise an interlevel dielectric layer over the nitride layer. Moreover, the nitride layer can be formed by bringing the temperature in a chemical vapor deposition reactor to below 550 degrees Celsius, placing the substrate into the reactor at the temperature, and forming the nitride layer on the substrate. Alternatively, the nitride layer can be formed by pushing the substrate into a chemical vapor deposition reactor at a speed greater than 300 millimeters per minute, and forming the nitride layer on the substrate.

High tensile nitride layer

Method of making a transistor having a deposited dual-layer spacer

Growing community of inventors

Portland, OR, United States of America

Raymond E Cotner