Microsoft Technology Licensing, LLC

Raymond D Pedrizetti

Curt Andrew Steeb

Paul C Sutton

Zeyong Xu

Martin Holladay

Munisamy Prabu

Daniel J Shapiro

Pierre-Yves Santerre

Michael Gallop

Scott D Quinn

Timothy W Bragg

Mukesh Karki

James Robert Benton

Kartik Nadipuram Raghavan

Jason T Cobb

W Jeff Westerinen

Thomas C Phillips

Alan R Morin

Task sequences are used to manage devices. According to one aspect, a user-defined or user-selected task sequence is received. The task sequence is converted into an ordered series of steps, and the series of steps are performed, in accordance with their order, in managing a device over a network. In certain implementations, the ordered series of steps are steps for automatically deploying an operating system on the device.

Using task sequences to manage devices

According to one aspect of task sequence interfaces, a method includes exposing an interface that allows task sequences to be performed on a plurality of remote devices, and receiving requests regarding the task sequences and the plurality of remote devices via the interface. The interface comprises an object model including device objects that represent physical devices in a network, and jobs objects that represent task sequences performed on one or more of the plurality of remote devices.

Task sequence interface

Multiple devices on which operating systems can be automatically deployed are managed. According to one aspect, an apparatus manages installation of operating systems on a plurality of computing devices. The installation is performed across the plurality of computing devices both concurrently and asynchronously.

Managing multiple devices on which operating systems can be automatically deployed

The present invention is directed to a peripheral device that integrally provides a program relating to the peripheral device, and may be connected to a computer system. The peripheral device includes a peripheral function subsystem for providing a peripheral device functionality. The peripheral device further includes a solid-state memory device storing a program relating to the peripheral device in a format used by disk drives. When the peripheral device is connected to a computer system, the program stored in the solid-state memory device is immediately available, and can be read by the computer system as though it was stored on a disk drive connected to the computer system.

Solid-state memory device that emulates a known storage device

An apparatus and method to automate the deployment, provisioning, and management of a programmable device for the life cycle states of the programmable device is presented. The system includes an automation interface for a developer to develop modules to aid in the automation of the deployment, provisioning, and management of the programmable device and for a user to direct the system to enter into a state of the life cycle. A controller moves the programmable device into states of the life cycle in response to triggering events occurring.

System and method to automate the management of computer services and programmable devices

A low bandwidth link can be used optimally for software updates, by successively transferring more information about the updates only as the likelihood of an applicable update successively increases. A many-to-one mapping function (e.g. a hash function) is applied to update identifiers on a server to generate a table of single bit entries corresponding to the updates. At a client, the same mapping function is applied to program identifiers to determine whether the server has a potential update. If a potential update is noted, a second transmission is requested for conveying additional data from the server by which hash collisions can be identified. A third transmission from the server is received conveying the actual update only after the availability of an actual update (versus a hash collision) is confirmed. The same arrangement can be employed in reverse.

Determining update availability via set intersection over a sub-optimal pathway

A duplicate memory image of the pages that need to be saved (i.e. hibernated) is created within volatile memory. The pages to be hibernated include all pages whose state is locked and a portion, if not all, of the pages whose state is idle. If the duplicate memory image of the pages to be hibernated cannot, however, be created due to a lack of volatile memory, a portion of the idle pages is pushed out to the swap file on secondary storage to free more volatile memory for this duplication. This duplicate memory image of the pages to be hibernated along with a corresponding page table identifying their location within volatile memory are then written out to a file on the secondary storage, completing hibernation and allowing the computer system to shut down in a hibernate mode.

Smart hibernation on an operating system with page translation

The present invention is directed to tracking and managing failure-susceptible operations in a computer system. In a preferred embodiment, the performance of failure-susceptible operations is monitored, such that, when execution of the operating system is interrupted then restarted, it can be determined which failure-susceptible operation was in progress at the point at which execution of the operating system was interrupted. In one embodiment, this monitoring is performed using a stack data structure. When a failure-susceptible operation is invoked, an entry is pushed on the stack identifying the invoked failure-susceptible operation. On the other hand, when a failure-susceptible operation is completed, the entry identifying the completed failure-susceptible operation is popped off the stack. The failure-susceptible operation that was in progress at the point at which execution was last interrupted is then determined to be the failure-susceptible operation identified by the top entry on the stack when execution resumes. In a further preferred embodiment, subsequent attempted invocation of the operation determined to be in progress when execution was interrupted is inhibited.

Tracking and managing failure-susceptible operations in a computer system

A set of software programs on a client computer is compared against a set of updates on a server computer to determine which updates are applicable and should be transferred from the server to the client. If the link between the client and server is slow, the listing of available updates must be represented in compact form. A many-to-one mapping function (e.g. a hash function) is applied to update identifiers to generate a table of single bit entries indicating the presence of particular updates on the server. This table is transferred to the client over the slow link. At the client, the same mapping function is applied to program identifiers, and corresponding entries of the transferred table are checked to determine whether the server has a potential update. If such a potential update is noted, a second transmission is requested by the client from the server--this one conveying additional data by which hash collisions can be identified by the client and disregarded. If availability of an actual update (versus a hash collision) is thereby confirmed, the client requests a third transmission from the server--this one conveying the actual update data. By this arrangement, optimized use is made of the low bandwidth link, with successively more information transferred as the likelihood of an applicable update is successively increased. (The same arrangement can be employed in reverse, with the bit table generated at the client and identifying program files available for possible updating, transferred to the server, etc.).

Determining program update availability via set intersection over a

The present invention provides a system and method for validating system address space for adapter cards having an information structure of a predefined format. Validation is accomplished by verifying the predefined format of the information structure via a memory window. Because verification is conducted via a memory window, it is only successful when the address space of the memory window is free of control by other components of the computer that would otherwise have interfered with verification. Thus, only a memory window that is suitable for adapter card allocation is validated.

Method and system for validating a memory window in system address space

A system for determining the connections between a PCMCIA controller and a programmable interrupt controller (PIC) by simulating an interrupt request from the PCMCIA controller and then evaluating the values contained in the interrupt request register of the PIC. An interrupt request association record is stored in response to receiving the simulated interrupt request at one of the interrupt request register inputs of the programmable interrupt controller. The interrupt request association record assigns the selected interrupt request line to the interrupt request register input that received the interrupt request signal. An interrupt request output from the PCMCIA controller is considered to be connected to a particular interrupt request register input of the PIC if a value in the interrupt request register of the PIC transitions from a logic low state to a logic high state, and then returns to the logic low state.

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Sammamish, WA, United States of America

Raymond D Pedrizetti