Bull Hn Information Systems, Inc.

Raymond D Bowden, Iii

Jeffrey S Somers

Marc E Sanfacon

George J Barlow

Chester M Nibby, Jr

Michelle A Pence

Edward R Salas

Richard A Lemay

A memory system coupled to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes circuits for storing the first address of an address sequence at the beginning of each burst operation and uses predetermined bits to generate any one of a set of address sequences as a function of the states of these bits. A first predetermined address bit is used to select different sequences of addressed readout data words to be transferred by the pair of DRAMs to the user. A second predetermined address bit is complemented to reverse two high order addressed word responses with two low order addressed word responses of specific address sequences. These operations are utilized in all of the required address sequences within different subgroups.

High speed burst read address generation with high speed transfer

A memory system tightly couples to a high performance microprocessor through a synchronous bus. The logic circuits included in the memory system generate a blipper pulse signal using successive transitions of clock pulse signals other than the edges used to synchronize microprocessor and memory operations. The blipper pulse signal is logically combined with the memory's column address strobe timing signal which is derived from the synchronizing edges of clock pulse signals which defines the duration of the column address interval required for accessing of a pair of DRAM memories during successive memory cycles for providing sequences of four memory read responses with no wait state.

High performance burst read data transfer operation

Memory retry logic to improve the resilience of system memory operations with respect to system errors or faults which prevent a memory read operation from being completed on a first attempt by allowing the memory to retry the operation once. The memory retry logic detects the occurrence of an improper response from the system element requesting a memory read operation when attempting to initiate the system bus operation for reading the data from memory to the requesting element and, if an improper response indicating that the requesting element is not accepting the bus operation request is detected, stores the memory operation request and the requested data and retries the data transmission on the next available bus cycle. If the memory receives an improper response of a specified type during a bus operation of a memory burst, the memory will terminate the operation and proceed to the next requested operation.

Method and apparatus for memory retry

A method and apparatus for resetting memory state when power is applied to the system. The memory has memory elements, a refresh clock and a refresh counter for counting refresh cycles and providing refresh signals to the memory elements, the memory elements and refresh means being connected from the power system and from a battery back-up means. A state detection means is connected from the refresh counter for detecting a change in state of the refresh counter to a state equivalent to the reset state of the refresh counter and asserting a state change signal. A means responsive to the state change signal and to the occurrence of the reset signal provides a memory controller reset signal, so that the memory controller reset signal occurs in synchronization with the change of state of the refresh counter to a state equivalent to the refresh counter reset state. The memory reset further includes a time-out counter means responsive to the assertion of the reset signal and to the refresh clock for counting refresh cycles in synchronization with the refresh counter. A time-out detection means is responsive to the time out counter means for providing a time out signal when the time-out counter has counted a refresh period plus one clock cycle and to the state change signal for providing the memory controller reset signal when the time-out counter has counted a refresh cycle plus one clock period and the state change signal has not been asserted.

Method and apparatus for resetting a memory upon power recovery

In accordance with the present invention, there is provided a system for logging an error that occurred in a multi-chip memory storage device in a data processing system. The system has a mechanism for detecting an error and for receiving data and check bits associated therewith. The mechanism for detecting an error generates syndrome bits as a function of the data and of the check bits. Connected to the error detecting mechanism is an error logging mechanism which is adapted to receive the syndrome bits and to determine the chip in which the error occurred.

Memory controller with error logging

A system and method for detecting an error that occurred in a multi-chip memory storage device in a data processing system. The system detects an error and receives data and check bits associated therewith. A process that uses the principle of scrubbing and incorporates high speed error flags distinguishes between hard and soft errors.

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Tewksbury, MA, United States of America

Raymond D Bowden, Iii