Burroughs, Inc.

Applied Micro Circuits Corporation

Raymond C Yuen

Bruce H Coy

Herbert Stopper

Mark A Menezes

The described embodiment of the present invention provides an output drive circuit having an input circuit comprising a differentially coupled pair of transistors. The output of the differentially paired transistors is provided to a pair of output driver transistors connected in a Darlington or a common collector-common emitter configuration which provides an output pull up signal to an output pin of the integrated circuit containing the described output driver. The opposite output of the differentially coupled pair is provided to a circuit which provides a pull down pulse to quickly shut off the transistor pair during the high to low transition of the output driver transistor. The use of the output driver transistor driver minimizes the current required by the differential pair and the fast pull down circuit eliminates the speed disadvantage of using a transistor pair output driver.

ECL output with Darlington or common collector-common emitter drive

In a multi-level ECL series gating circuit with three levels of gating which operates over specified operating circuit voltage and operating circuit temperature ranges, provision is made for stabilizing the magnitude of the circuit source current over the operating voltage and temperature ranges by regulating the bias voltage which determines the circuit source current. The bias voltage is regulated according to the inverse of the operating temperature to account for the temperature characteristics of the base-to-emitter diode in the transistor generating the circuit current. The magnitude of the bias voltage over the temperature range never reaches a level which will send the circuit current transistor into saturation at any circuit voltage in the operating range.

Multi-level ECL series gating with temperature-stabilized source current

A circuit for translating TTL-to-ECL-type signals utilizes an unbuffered emitter-coupled transistor pair for shifting signal levels. The emitter-coupled transistor pair operates by switching a current from a current-source transistor, with the switching being performed against a temperature-compensated threshold voltage that is derived from a reference voltage provided to the current source transistor. Direct, unbuffered switching of the emitter-coupled transistor pair insures rapid, symmetrical response to the TTL signals that drive the transistor pair and produces high-quality, relatively undistorted ECL waveforms. Provision of a current-source reference voltage stabilized with respect to temperature also contributes to reduction of distortion in the ECL waveforms. The threshold voltage is obtained from the current source reference voltage through a current mirror circuit.

Unbuffered TTL-to-ECL translator with temperature-compensated threshold

A circuit for controlling flip-flop hold and set-scan operations responds to one state of a HOLD/PASS signal by blocking the provision of a flip-flop CLOCK signal to one or more flip-flops which are to conduct a holding operation. The circuit responds to the pass state of the HOLD/PASS signal by permitting the flip-flop clock to be provided to the control flip-flops so that they can conduct shift or pass operations.

Flip-flop control circuit

Circuitry for programming a read-only memory comprising a plurality of decoding transistors of low current density for selecting the row of the programmable matrix and which function to operate a high current density control transistor through a large voltage swing for controlling an output transistor of the circuitry connected directly to the array. The decoding transistors are operable through a CML voltage swing in a non-saturated mode with minimum current to operate the control transistor of high current density from cut-off to saturation to turn the output transistor ON or OFF which in turn directs the high voltage from a high voltage source to the programmable memory.

Decoder for a prom

A voltage regulator and regulator buffer having a plurality of matched transistors including an output transistor arranged such that the fluctuation in supply voltage is sensed by a shunt circuit which tracks such voltage fluctuation and eliminates such fluctuations from the output transistor by causing current variations due to supply voltage variations to flow through another transistor connected in parallel with the output transistor thus eliminating the first order effects of power supply voltage variations on output voltage. The voltage regulator buffer comprises a plurality of matched transistors which also has a voltage supply variation shunt circuit similar to the regulator shunt circuit to regulate the current through an output transistor thus eliminating the effect of the power supply voltage thereon and providing an output voltage of a precise amount.

Voltage regulator and regulator buffer

An In-Situ Test and Diagnostic Circuit and Method to monitor the integrity of external connections of a current mode logic integrated circuit chip (inputs and outputs) as well as the integrity of the logic function thereof. The circuit comprises three parts: an 'Open' Input Detector to detect open connections or connections that are becoming open between one chip and another; an Output Short Detector to monitor shorts at any chip output; and a Signature Test and Diagnostic circuit to determine if the logic function of the chip itself is operational. All the foregoing circuit parts are formed as an integral part of each CML chip and connected to an output terminal called a Test and Diagnostic Pin.

In-situ test and diagnostic circuitry and method for CML chips

A duplex driver/receiver module having circuitry which permits the sending and receiving of data from an identical module simultaneously, utilizing resistive and gating techniques to overcome differential noise, to accommodate circuit manufacture process variations and transmission line resistances within the CML logic environment.

Growing community of inventors

San Diego, CA, United States of America

Raymond C Yuen