Teledyne Industries, Inc.

Telcom Semiconductor, Inc.

Teledyne Semiconductor

Raymond C Yan

Bruce A Rosenthal

Richard L Gray

A battery charger including a battery detector at a node at which a battery is connectable. When a battery is not present, a voltage at the node fluctuates, but when a battery is present, the battery holds the voltage substantially constant. A level shifter shifts the voltage at the node. If no battery is present, the shifted voltage will fall below a predetermined threshold, but if a battery is present, the shifted voltage will remain above the predetermined threshold. A ground sense comparator detects whether or not the shifted voltage is below the predetermined threshold, and provides a battery detection signal accordingly. A controllable charge driver couples power from a power supply through to a battery, to charge the battery. An integrated circuit provides logic functions of the apparatus, including logic functioning as a charge controller. The charge controller is responsive to the battery detection signal to provide a charge drive signal to turn on the controllable charge driver only if a battery is present. The battery charger is capable of fast charging a wide variety of batteries according to a user-selectable charge rate.

Battery charger with battery detection circuit

In an input buffer, logic level discrimination is provided by a first circuit which provides a first current to the output so that the output voltage is a hysteresis function of the input volt. To improve transient response without increasing power consumption, a second circuit is used to provide a second current to the output in support of the first current during transient periods of the input signal.

Logic level discriminator

A differential input amplifier having adjustable quiescent output voltage is provided by connecting a current means which, responsive to an adjustment voltage, can introduce current into and remove current out of one of the current paths of the amplifier.

Offset compensated amplifier

A level discriminating buffer, including a input stage, a latching stage, and a switching accelerator, having an improved response time. The input stage discriminates between logic states of the input signal. The latch stage acts as a logic state latch and further provides transistors in the current paths of the input and latch stages that are non-conducting during each static state of the input signal. The switching accelerator is responsive to the input stage for generating a short period signal to accelerate the logic state switching of the latch stage and thereby improve the response of the output signal to a change in an input signal logic state change.

Zero static current high speed TTL compatible buffer

An electrical switch network having a substantially reduced effective ON-resistance is provided. The electrical switch network includes an input amplifier receiving the input signal at one input, and a first switch having a first terminal connected to the output of the input amplifier and a second terminal connected to a device, such as an integrator circuit, which is to receive the amplified input signal. Two additional switches are connected between a respective terminal of the first switch and a second input of the input amplifier. A pulse signal generator controls the conductive state of the switches such that the first and third switches are in a complementary conductive state with respect to the second switch. The conductive resistance of the second switch is preferably chosen to be equal to or greater than the combined conductive resistance of the first and third switches.

Reducing resistive effects of an electrical switch

In a circuit for providing a bandgap voltage reference, a first current proportional to the thermal voltage V.sub.T is generated by a first current source. By means of current mirror operation, the first current induces a second current source to generate a proportional second current. The second current source is coupled to means which generates a first voltage which is proportional to the base-emitter junction of a bipolar transistor. The second current generates a second voltage which is then added to the first voltage to give the voltage reference.

CMOS compatible bandgap voltage reference

An ESD protection circuit, suitable for use as part of an integrated circuit, limits the voltage potential at the contacts of the integrated circuit to a voltage potential difference range relative to, though extending beyond the voltage source potentials of the circuit protected. The ESD protection is effective regardless of whether the integrated circuit is powered. The ESD protection circuit includes a clamp subcircuit for limiting the voltage potential at a clamp point to a first voltage range approximately defined by the voltage source potentials and a voltage offset subcircuit, coupled between the clamp point and an integrated circuit contact, to establish a second voltage range encompassing the first voltage range. The voltage offset subcircuit conducts current between the clamp point and the contact to limit the voltage potential at the contact to the second voltage range.

ESD protection circuit for MOS integrated circuits

The present invention provides a precision current source wherein a reference current level is established by the inter-dependent operation of three current stages. The first stage provides first and second current paths and functions to mirror the current level through the first and second current paths. A second stage, coupled to the first and second current paths, defines a first current/voltage relationship at respective points in the first and second current paths. A third stage, also coupled to the first and second current paths, defines a second current/voltage relationship again at the respective points in the first and second current paths. In accordance with the present invention, the first and second current/voltage relationships are chosen to be mutually solvable for a discrete, non-zero pairing of voltage and current levels, thereby establishing a reference current level at the defined current set point.

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Daly City, CA, United States of America

Raymond C Yan