Xilinx, Inc.

Xilink, Inc.

Raymond C Pang

Stephen M Trimberger

Steven P Young

Jennifer Wong

Kwansuhk Oh

Trevor J Bauer

F Erich Goetting

Walter N Sze

Glenn A Baxter

Kiran B Buch

Edwin S Law

Kameswara K Rao

Hsung Jai Im

Sunhom Paak

John M Thendean

Bruce E Talley

Jan Lodewijk De Jong

Venu M Kondapalli

Paul Ying-Fung Wu

Thanh Ngoc Pham

Alvin Y Ching

Boon Yong Ang

Scott O Frake

Jane W Sowards

P Hugo Lamarche

Patrick J McGuire

Susan Xuan Nguyen

Peter H Alfke

Schuyler E Shimanek

Andrew K Percey

Robert M Ondris

Serhii Tumakha

Shawn K Morrison

An electronic fuse memory array has an array core with a plurality of selectable unit cells. A unit cell has a fuse and a cell transistor (M). A programming current path goes through the fuse and the cell transistor to a word line ground and a read current path also goes through the fuse and the cell transistor to the word line ground.

Electronic fuse array

A memory cell having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value has an aspect ratio of at least 5:1. The high aspect ratio provides adequate spacing between nodes of the memory cell for SEU tolerance at small design technologies.

Memory cell with single-event-upset tolerance

An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in evaluation wafers to determine proper efuse fabrication and programming parameters, and in production ICs to identify efuse programming damage that might create a latent defect.

Integrated circuit with fuse programming damage detection

A clock manager circuit includes a number of clock output blocks, each providing an independent output. Counter controlled delay devices (CCDs) are used in these clock output blocks. To achieve full cycle delays, the CCDs are placed in parallel with outputs of the CCD outputs driving set and reset terminals of a common latch. The parallel connection of the CCDs, as opposed to a series connection, offers an increase in maximum frequency and possibly fewer needed CCDs than if the CCDs are placed in series. In one embodiment, at least one of the CCDs includes a counter/compare circuit with a frequency divider enabling the frequency of the CCD to be varied relative to the common input clock.

Circuits and methods of using parallel counter controlled delay lines to generate a clock signal

A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset ('SEU') tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.

Interleaved memory cell with single-event-upset tolerance

An eFuse sensing circuit replaces the inverters used to provide the 'read' output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.

eFuse resistance sensing scheme with improved accuracy

An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.

Yield-enhancing methods of providing a family of scaled integrated circuits

An integrated circuit having a scalable boundary scan architecture. Logic elements, each including at least one data storage element, are arranged in rows and columns. A data distribution system couples the data storage elements together to form a boundary scan chain that traverses the columns in order, e.g., a first column, then a second column, and so forth, from top to bottom in each column. A clock distribution system is coupled to each of the data storage elements in the chain, and provides a clock signal to the first and second columns, again from top to bottom. The clock distribution system provides the clock signal to the top of the second column prior to providing it to the top of the first column. In some embodiments, an additional flip-flop is added to the boundary scan chain for each logic element, to increase the overall operating frequency of the scan chain.

Scalable columnar boundary scan architecture for integrated circuits

A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.

Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes

A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.

Multi-product die configurable as two or more programmable integrated circuits of different logic capacities

According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

Circuit for and method of implementing a content addressable memory in a programmable logic device

Memory device and method of transferring data in memory device

A trim unit includes a delay line and one or more individually selectable load elements. The delay line has a first end to receive an input clock signal, and has a second end to generate an output clock signal. Each load element includes a select transistor and a load capacitor coupled in series between the delay line and ground potential, and includes a filter circuit having an input to receive a select signal and having an output coupled to a gate of the select transistor. Upon assertion of each select signal, the filter circuit gradually charges the gate of the select transistor, which in turn causes the load element to gradually increase the phase-delay between the input and output clock signals.

Trim unit having less jitter

A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a set of clock lines. The trim delay structure also includes a capacitive trim unit having a plurality of capacitive trim elements tapped off the set of clock lines. The capacitive trim elements are selectively enabled or disabled, thereby introducing additional delay to the delayed clock signal on the set of clock lines. Each capacitive trim element can include a transmission gate structure, which is turned on to introduce significant junction capacitance to the set of clock lines. The trim delay structure can also include a second buffer adapted to buffer the delayed clock signal on the set of clock lines.

Digital clock manager capacitive trim unit

It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.

Growing community of inventors

San Jose, CA, United States of America

Raymond C Pang