Visteon Global Technolgoies, Inc.

Linear Technology Corporation

Linear Technology Holding LLC

Visteon Corporation

Raymond Allen Stevens

Samuel James Guido

Martin G Gravenstein

Rollie Morris Fisher

Robert L Anderson

Kevin Michael Rishavy

Gary Thomas Bastian

Kalin Valeriev Lazarov

Edson Wayne Porter

Matthew Joseph Maloney

Michael David Petersen

Methods and systems of synchronizing events using a plurality of sequencing controllers are provided. For each sequencing controller, a serial communication bus (SCB) is monitored for a first reference level. Upon identifying that the SCB is at the first reference level for a predetermined period, a bit sequence indicative of an event position is broadcast to be arbitrated on the SCB. The SCB is monitored for the arbitrated bit sequence. Upon determining that the arbitrated bit sequence corresponds to the bit sequence of the event position, an event corresponding to the event position is enabled.

Coordinated event sequencing

A power control system includes an event data bus configured to carry event information. Several power supply managers are coupled to the same event bus. Each power supply manager has one or more point of load (POL) regulators assigned to it. Each power supply manager communicates event information with other POL power supply managers over the event data bus.

Power supply system and method

A controllerhas an I/O crossover switching network, an optional I/O network expansion, a plurality of serial I/O shifters, a clock generatorand I/O control logic. The I/O crossover-switching networkis also referred to as an I/O multiplexer. Serial data may be transferred between a serial I/O shifter and an external device by way of a dedicated serial data pin (SDATA)or an optional alternate pathwaywhich uses one of a plurality of parallel pins. The optional alternate pathwaycan be used when pinsare unavailable or to reduce the number of pins on the device. The controller is shown to communicate with an external devicealso having parallel pins. While a single deviceis shown, the external devicecan be any number of a plurality of devices having serial and parallel signal pathways that is controlled by the microprocessorof the present invention.

I/O multiplexer and pin controller with serial and parallel capabilities for microprocessor based engine control

A data queue control submodule supporting a host processor and at least one peripheral device. The submodule includes a memory unit with a first memory portion for storing queue commands associated with each peripheral device and a second memory portion for storing peripheral device data. A queue control unit is also included in the submodule for controlling the flow of data between the peripheral devices and the host processor in accordance with the queue control commands. A port interface connects the queue control unit and the peripheral devices in response to a trigger event. The submodule further includes an event controller in communication with the host processor and the port interface for generating event triggers in response to data demands of either the host processor or the other peripheral devices. The present invention is advantageous in that it simplifies the design of each port interface and provides improved flexibility in the queue structure of the overall control system.

Queued port data controller for microprocessor-based engine control applications

An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.

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Monument, CO, United States of America

Raymond Allen Stevens