General Electric Company

Martin Marietta Corporation

Other

Lockheed Martin Corporation

Momentive Performance Materials Gmbh

Raymond Albert Fillion

Kaustubh Ravindra Nagarkar

Robert J Wojnarowski

Kevin Matthew Durocher

William Edward Burdick, Jr

Christopher James Kapusta

Paul Alan McConnelee

Ronald Frank Kolc

Risto Ilkka Sakari Tuominen

Herbert S Cole

Charles S Korman

Charles Gerard Woychik

Ernest Wayne Balch

Richard Alfred Beaupre

Wolfgang Daum

James Wilson Rose

Richard J Saia

Thomas Bert Gorczyca

Eric J Wildi

James F Burgess

Donald W Kuk

Jesse Berkley Tucker

Arun Virupaksha Gowda

Stephen Daley Arthur

Ahmed Elasser

Eladio Clemente Delgado

David Joseph Kachmarik

Leonard Richard Douglas

Michael Gdula

Laura Jean Meyer

Peter N Bronecke

Joshua Isaac Wright

Anil Raj Duggal

William P Kornrumpf

Charles Dominic Iacovangelo

Thomas Frederick Soules

Glenn Scott Claydon

Sayed-Amr A El-Hamamsy

William Hullinger Huber

Steven Marc Gasworth

Otward M Mueller

Bernard Gorowitz

Constantine A Neugebauer

Jozsef Fulop

Ferenc Papp

Istvan Wursching

Sandeep Shrikant Tonapi

Robert S McFeely

Davide Louis Simone

Barry Scott Whitmore

Michael W DeVre

Kelvin B Belle

Elizabeth Ann Burke

Donald Stephen Bitting

Walter M Marcinkiewicz

Erwin G Steinbrenner

Leon F Chamberlain

Hong Zhong

Eugene L Bartels

Albert Andreas Maria Esser

Rob Ert John Wojnarowski

Edward S Bernard

Barry S Whitmore

Robert J Woinarowski

Daniel Lee Abraham

Richard Joseph Saia

Charles Gerard Woychick

Robert John Wojnarowski

Charles Steven Korman

Donald William Kuk

A phased array antenna system comprising a plurality of isotropic radiating elements and/or omnidirectional receiving elements addressing close in fields and a plurality of non-isotropic radiating elements and/or non-omnidirectional receiving elements addressing remote fields with the combined elements used to extend the maximum range of the antenna system without increasing the number of element nor the output power of the antenna. The non-isotropic radiating elements and/or the non-omnidirectional receiving elements can be formed by adding focusing structures such as lenses or reflective structures in the radiating path of isotropic radiating elements and/or omnidirectional receiving elements. Antennas with combined isotropic radiating and non-isotropic radiating elements can be utilized for electromagnetic phased array radar, communication and imaging systems and for acoustic phased array sonar or ultrasound systems.

Phased array antenna with isotropic and non-isotropic radiating and omnidirectional and non-omnidirectional receiving elements

A phased array antenna system comprising: a first plurality of array elements, each array element in the first plurality comprising a radiating element having a generally isotropic radiating pattern and/or a receiving element having a generally omnidirectional field of view; and a second plurality of array elements, each array element in the second plurality comprising a radiating element having a non-isotropic radiating pattern and/or a receiving element having a non-omnidirectional field of view; wherein: the generally isotropic radiating pattern comprises a field of at least 120&#xb0; in azimuth and 90&#xb0; in elevation; the generally omnidirectional field of view comprises a field of at least 120&#xb0; in azimuth and 90&#xb0; in elevation; the non-isotropic radiating pattern comprises a field of less than half of the field of the generally isotropic radiating pattern in azimuth and/or elevation; and the non-omnidirectional field of view comprises a field of less than half of the field of the omnidirectional field of view.

An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof

An acoustic phased array antenna system comprising a plurality of omnidirectional receiving elements for addressing close-in fields and a plurality of non-omnidirectional receiving elements for addressing remote fields with the combined elements used to extend the maximum range of the antenna system. The non-omnidirectional receiving elements can be formed by adding focusing structures such as cylindrical or oval lenses in the receiving path of omnidirectional receiving elements. Antennas with a plurality of isotropic radiating and a plurality of non-isotropic radiating elements can be utilized for sonar and ultrasound systems. An acoustic phased array antenna system comprising a first plurality of receiving elements with a first field of view and a second plurality of receiving elements with a second field of view that is at least 50% narrower. An acoustic phased array with a plurality of isotropic radiators and a plurality of non-isotropic radiators to extend the range of the system.

Acoustic phased array antenna with isotropic and non-isotropic radiating elements

An electronics package includes an insulating substrate, an electrical component having an active surface coupled to a first surface of the insulating substrate, and an insulating structure disposed adjacent the electrical component on the first surface of the insulating substrate. A first wiring layer is formed on a top surface of the insulating structure and extends down at least one sloped side surface of the insulating structure. A second wiring layer is formed on a second surface of the insulating substrate. The second wiring layer extends through a plurality of vias in the insulating substrate to electrically couple at least one contact pad on the active surface of the electrical component to the first wiring layer.

Electronics package with integrated interconnect structure and method of manufacturing thereof

An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.

An electronics package includes a multilayer interconnect structure comprising insulating substrate layers and conductor layers. The electronics package also includes an electrical component comprising I/O pads electrically coupled to the conductor layers and conductive through vias extending through at least two insulating substrate layers and electrically connected to at least a portion of the I/O pads. The conductor layers include a first conductor layer including a ground plane buried in the multilayer interconnect structure, the ground plane forming direct electrical and physical connections with a conductive through via electrically connected to a ground I/O pad of the plurality of I/O pads. The conductor layers also include a second conductor layer including a power plane buried in the multilayer interconnect structure, the power plane forming direct electrical and physical connections with a conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.

Multilayer interconnect structure with buried conductive via connections and method of manufacturing thereof

A reconfigured semiconductor logic device includes a semiconductor logic device comprising a plurality of input/output (I/O) pads formed on an active surface thereof and a redistribution layer. The redistribution layer comprises an insulating layer formed atop the active surface of the semiconductor logic device such that the insulating layer does not extend beyond an outer perimeter of the active surface and a patterned conductive wiring layer positioned above the insulating layer. The patterned conductive wiring layer includes a plurality of terminal buses formed on a top surface of the insulating layer. Each terminal bus of the plurality of terminal buses is electrically coupled to multiple I/O pads of the plurality of I/O pads through vias formed in the insulating layer.

Semiconductor logic device and system and method of embedded packaging of same

An electronics package is disclosed that comprises a multilayer interconnect structure including a plurality of insulating substrate layers each having a plurality of microvias formed therein, a plurality of conductive wiring layers positioned on the plurality of insulating substrate layers, and a plurality of conductive microvias in the plurality of microvias to, wherein a bottom wiring layer includes a plurality of first terminal pads that are positioned on a bottom surface of the multilayer interconnect structure. The electronics package also comprises an electrical component coupled to the bottom surface of the multilayer interconnect structure, the electrical component including first I/O pads aligned with the first terminal pads and second I/O pads aligned to regions of the multilayer interconnect structure without first terminal pads. The electronics package further comprises a plurality of conductive through vias extending through the multilayer interconnect structure and electrically connected to the plurality of second I/O pads.

Device almost last embedded device structure and method of manufacturing thereof

An embedded electronics package and method of manufacture includes a support substrate, a power semiconductor component coupled to a first side of the support substrate, and a logic semiconductor component coupled to a second side of the support substrate, opposite the first side. A first insulating material surrounds the logic semiconductor component. A logic interconnect layer is electrically coupled to the logic semiconductor component by at least one conductive micro-via extending through a portion of the first insulating material. A power interconnect layer is electrically coupled to the power semiconductor component by at least one conductive macro-via extending through a thickness of the support substrate. The power interconnect layer is thicker than the logic interconnect layer.

Embedded electronics package with multi-thickness interconnect structure and method of making same

A reconfigured semiconductor logic device includes a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon and a redistribution layer. The redistribution layer includes an insulating layer disposed on the active surface of the semiconductor logic device and a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer. The plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer. The plurality of discrete terminal pads are larger than the plurality of I/O pads.

A method of manufacturing a multi-layer electronics package includes attaching a base insulating substrate to a frame having an opening therein and such that the frame is positioned above and/or below the base insulating substrate to provide support thereto. A first conductive wiring layer is applied on the first side of the base insulating substrate, and vias are formed in the base insulating substrate. A second conductive wiring layer is formed on the second side of the base insulating substrate that covers the vias and the exposed portions of the first conductive wiring layer and at least one additional insulating substrate is bonded to the base insulating substrate. Vias are formed in each additional insulating substrate and an additional conductive wiring layer is formed on each of the additional insulating substrate. The described build-up forms a multilayer interconnect structure, with the frame providing support for this build-up.

Method of manufacturing an electronics package using device-last or device-almost last placement

Growing community of inventors

Niskayuna, NY, United States of America

Raymond Albert Fillion