Westinghouse Electric Corporation

Raymond A Lloyd

Kenneth C Ryan

Kenneth E Daggett

Michal M Feilchenfeld

Larry L Charles

William F Susie

William L Hrybyk, Deceased

James R Reeder

Allen W Tate, Jr

Theodore B Stagg, Jr

Robert Martinez

Thomas A Keller

Derek B Eckert

An automatic test system controlled by a general purpose digital central processor is disclosed. The central processor accepts test programs in a high level compiler language such as Atlas. The Atlas program is compacted into a simplified language which is utilized to communicate with test devices via a standard IEEE 488 data bus. Each of the test devices includes a programmable interface digital processor which performs any translation that may be necessary in order to permit specific test instruments coupled to the central processor via the interface processor to perform the tests specified by the high level test programs. A switching matrix also communicates with the digital processor to connect the appropriate test device to the unit under test.

Automatic test system utilizing interchangeable test devices

A test system utilizing a plurality of programmable test instruments each capable of executing portions of a test program with the test program being written in a compiler language such as ATLAS, for example, is disclosed. Programs specifying the tests to be performed are written in a compiler language such as ATLAS and transferred to a central control processor utilizing standard peripheral equipment. The central control processor communicates with a plurality of test instruments utilizing a series of data busses. In executing the test program, the control processor first segments the program into a series of individual tests to be performed. The test instruments are interrogated to determine which of the test instruments is currently capable of executing a specific sequence of the test program. Once an instrument has been identified which can execute the program segment, the control process transfers that segment to the instrument capable of executing the test. After a test has been executed, the programmable test instrument executing the test transfers the result of the test back to the central control processor for analysis. In addition to performing the basic test, each of the instruments also has access to the switching matrix so that the required interconnects between the system being tested and the test instruments can be made under the control of the test instrument itself. Functionally, each of the test instruments accepts segments of the overall test program in a compiler language and performs all the functions necessary to execute that segment of the program and transfer the test results to the central processor. The function of the central processor is to control the system, allocate portions of the program to each of the test instruments and analyze the final test result. Alternate embodiments provide means permitting any one of the programmable test instruments to assume control of the entire system.

Multi-processor automatic test system

A monitoring circuit for digital circuits is disclosed. The monitor is primarily applicable to digital circuits which operate in a cyclic mode with the digital patterns generated during each cycle being repeated in a predictable manner. A predetermined number of expected bit patterns are stored in a programmable memory. The stored bit patterns correspond on a bit-by-bit basis to the bit patterns generated by the circuit being monitored when this circuit is operating normally. In the self-scan mode each pattern generated by the circuit being monitored is compared to each of the patterns stored in the memory in a sequential manner. Each time a pattern generated by the circuit being monitored is found to identically correspond to a pattern stored in the memory a valid pattern pulse is generated which steps a down counter one count. If this process does not result in the down counter being stepped the expected number of times during the operating cycle, a flip-flop is set indicating that the circuit being monitored has malfunctioned. Provisions are also included for counting the transitions of a digital signal during predetermined portions of the cycle of the circuit being monitored and for monitoring the polarity and amplitude of a predetermined number of analog voltages. The result of all of these tests are combined to generate a signal indicating the operational status of the circuit being monitored. The monitoring circuit may also be operated in a one-to-one correspondence mode. In this mode each bit pattern generated by the circuit being monitored are compared to bit patterns stored in a selected memory location. If these bit patterns are not identical, a malfunction signal is generated.

Monitoring circuit

A digital monitor for monitoring the operation of a synchronous digital system. Proper operation of the monitored digital system is determined by storing a predetermined sequence of digital numbers in a memory. The bit patterns generated by the system being monitored are utilized as addresses to read the stored digital numbers. After each read cycle the digital number read from the memory is examined to determine if it has the proper value. If the value is not proper, a memory is set indicating that the system being monitored has malfunctioned. Additionally, the number of bit patterns checked during each cycle of the system is determined. If the correct number of patterns are not checked, the memory is also set indicating that a malfunction has occurred. Apparatus for monitoring a selected number of analog signals such as power supply voltages is also provided. Either of these tests may be inhibited by signals from the system being monitored or by signals from an external source.

Digital monitor having memory readout by the monitored system

A system for evaluating members or a family of similar devices by comparing images of a model device to the image of the member to be evaluated is disclosed. An image of the model device is first produced and stored in a memory. An image of the member to be evaluated is produced as the stored image of the model device is simultaneously reproduced. The images of the model and the member being evaluated are compared to generate a comparison signal related to the differences therebetween. The comparison signal is sampled at a predetermined rate, to produce a digital signal indicating sample points where the comparison signal exceeds a predetermined value. Statistical techniques are used to analyze the digital signal to determine which portions of this signal correspond to significant differences between the images of the model device and the member being evaluated. The portions of the digital signals corresponding to significant differences between images of the model and device being evaluated are combined with the image of the device being evaluated to produce a multicolor composite image. In the composite image areas of the image of the device being evaluated which are significantly different from the image of the model device are displayed in red with the remainder of the composite image being green.

Sampled differential analyzer

A system for evaluating similar object by comparing an image of the objects to be evaluated to the image of a similar object is disclosed. The system utilizes a TV camera to generate and store in a video memory an image of a reference member of the family of objects to be evaluated. This reference member has been previously evaluated by other means to determine that it meets predetermined specifications. An image of the member to be evaluated is then generated by focusing the TV camera on this member. Simultaneously, the stored image of the reference member is read from the video memory. These two images are compared to each other by an analog circuit to generate an analog signal related to the difference between these two signals. Sync signals are also generated by the memory to control the TV camera and a line counter which indicates which lines of the TV images are being compared. The line counter controls a digital memory to read stored digital data identifying the lines of the TV images to be used in evaluating the object being examined. The analog signal is analyzed to generate pulses. The width of each of the pulses is related to the amplitude and time duration of the difference between the lines of the TV images. If the width of this pulse exceeds a predetermined duration an error signal is generated indicating that the object being evaluated does not comply with predetermined specifications. Alternatively, the system may be modified to require the detection of significant errors in at least two adjacent scan lines before an error signal is generated.

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Laurel, MD, United States of America

Raymond A Lloyd