Sun Microsystems, Inc.

Other

Oracle America, Inc.

Fairchild Semiconductor Corporation

Intergraph Corporation

Raymond A Heald

Claude R Gauthier

Michael A Ang

Shaishav A Desai

Peter F Lai

Rambabu Pyapali

Xuejun Yuan

Xiaowei Jin

James M Kaku

Roger Y Lo

Aharon Ostrer

Thelma C Taylor

Helen Dunn

Wen-Jay Hsu

Robert J Proebsting

Pradeep R Trivedi

Edgardo F Klass

Venkatesh P Gopinath

Gin S Yee

Chaim Nmi Amir

Steven R Boyle

Anand Dixit

David Hugh McIntyre

Paul J Dickinson

Raoul B Salem

Hua-Yu Su

David W Poole

Lik Cheng

Suresh Seshadri

Gurupada Mandal

Subramanian Ganesan

Vernon R Brethour

Vernon Brethour

William Y Mo

Shih-Huey Wu

A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.

Method for monitoring and adjusting circuit performance

A novel scheme for screening weak memory cell includes a cell coupled to a leakage stress delivery circuitry (LSDC), which, in turn, is coupled to an induced leakage adjustment control (ILAC). The LSDC includes a combination of PMOS transistors, NMOS transistors or both PMOS and NMOS transistors that are controlled by a plurality of stress inducing signals. The PMOS and/or NMOS transistors of the LSDC are coupled to a pair of complementary data lines. The complementary data lines are inputs to a sense amplifier and are outputs of a write driver. The ILAC controls the quantity of the leakage stress applied through the LSDC to the pair of complementary data lines. The ILAC further includes a leakage varying circuitry that is configured to adjust the leakage stress applied to the complementary data lines through the LSDC. The applied leakage stress is adjusted to establish a desired pass/fail threshold and to detect other process variations or defects so that the sense amplifier can be applied to detect the voltage differential during a read operation. The applied leakage stress can also be applied to write driver circuitry such that a write driver along with the applied stress provide enough voltage level to screen difficult-to-write cell from a easy-to-write cell during a write operation. The plurality of stress inducing signals are controlled such that the appropriate leakage stress may be applied to force a leakage to Vdd or Vss associated with the cell through the complementary data lines.

Scheme for screening weak memory cell

An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one embodiment of the present invention, a two-stage sensing scheme is implemented. The improved fuse sensing circuit uses current-mode sensing and implements an auto-read current reduction scheme. Using a level-detect circuit, the virtual ground is raised automatically if the high-voltage power supply exceeds core supply (Vdd) by a fixed dc voltage. This reduces effective sensing voltage and the read current and thus helps preserve unblown fuse integrity. In one embodiment of the invention, four modes of operation are implemented: 'Normal Read,' 'Unblown_Read,' &#x201c;Blown_Read_1&#x201d; and &#x201c;Blown_Read_2.&#x201d; The default read mode is the &#x201c;normal read&#x201d; while the &#x201c;Unblown&#x201d; and &#x201c;Blown&#x201d; read modes are for fuse calibration purposes. In the &#x201c;Unblown_Read&#x201d; read mode, the circuit is operable to compare the fuse resistance against a lower reference resistance, closer to an unblown fuse resistance value, in order to make the comparison more stringent. Similarly, the &#x201c;Blown_Read_1&#x201d; and &#x201c;Blown_Read_2&#x201d; modes allow a more stringent comparison for a blown fuse resistance.

Fuse sensing scheme with auto current reduction

A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Sense amplifier thermal correction scheme

A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

Compensation technique to mitigate aging effects in integrated circuit components

Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug

A method of continuously replenishing a four-transistor static RAM storage cell is described. Such method comprises biasing both the back gate terminals and the normal gate terminals of the two bit line coupling transistors in the static RAM storage cell to voltage levels for causing a flow of small compensating currents through such coupling transistors when they are in a standby or non-access condition. Such small compensating currents are supplied to the two storage transistors in the storage cell for replenishing leakage of charge from the parasitic capacitance in the storage cell. The bias voltages are supplied by adaptive bias circuits which adjust the bias voltages to track changes in the leakage of charge from the parasitic cell capacitance.

Static random access memory (RAM) systems and storage cell for same

A method of continuously replenishing a four-transistor static RAM storage cell is described. Such method comprises biasing both the back gate terminals and the normal gate terminals of the two bit line coupling transistors in the static RAM storage cell to voltage levels for causing a flow of small compensating currents through such coupling transistors when they are in a standby or non-access condition. Such small compensating currents are supplied to the two storage transistors in the storage cell for replenishing leakage of charge from the parasitic capacitance in the storage cell. The bias voltages arc supplied by adaptive bias circuits which adjust the bias voltages to track changes in the leakage of charge from the parasitic cell capacitance.

The present invention relates to a method and apparatus for efficiently outputting words from an N-way set-associative cache. In one embodiment, the cache tags contain information indicating which set contains a line holding data succeeding the last word in the line accessed during a cache read. For a cache which outputs M words for each access, when the addressed word is within M-1 words of the end of the line, the cache will output all the words from the accessed word to the end of the line and the remainder of the M words from a succeeding line in whatever set is indicated by the pointer.

Method and apparatus for fetching information from a cache memory

A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data put signal. The first and second input latches have first and second shutoff circuits, respectively. During a precharge phase, the first and second input latches each provide an output signal of a first logic level. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal, respectively. In response to the samples of true and the complement of the data input signal, one input latch's output signal will transition to a second logic level, while the other input latch's output signal will remain at the first logic level. A first output latch and a second output latch are coupled to receive the output signals of the first and second input latches, respectively. The first and second output latches are inverting. During the precharge phase, the flip-flop provides output signals of the second logic level from both of the output latches. During the evaluation phase, one output latch will continue to provide an output signal of the second logic level and the other output latch will provide an output signal that transitions from the second logic level to the first logic level.

Edge-triggered dual-rail dynamic flip-flop with self-shut-off mechanism

A method is provided for accurately determining the propagation delay of a gate under consideration in a static timing analyzer. This is accomplished by determining both the output load and input rise time of the gate under consideration. These values are then compared with a load versus rise time grid having previously determined values of propagation delay (points) for specified combinations of load and input rise time. These points are then used to interpolate a value of propagation delay for the gate under consideration by an interpolation technique that accounts for at least one of the following non-linear effects: the feed forward capacitance of a gate, soft switching, gate resistance, source and drain resistance, and/or other non-linear effects. The method accounts for each non-linear effect by imparting a corresponding component to propagation delay only in that range of output load and input rise time for which that non-linear effect is most pronounced.

Method of determining signal propagation delay through circuit elements

A clock generator generates repetitive master clock pulses, each master clock pulse having a leading edge and a trailing edge. The time interval between the leading edge of a first master clock pulse and the leading edge of a second master clock pulse defines a single clock cycle. A write pulse generating circuit generates write pulses for writing data into a multi-port RAM, and a read pulse generating circuit generates read pulses for reading data from the RAM. When simultaneous reading and writing of data is requested in a particular clock cycle, the leading edge of the write pulse is generated in response to the leading edge of the first master clock pulse before the leading edge of the second master clock pulse. The leading edge of the read pulse is generated after the leading edge of the write pulse, such that the data written into the memory can be read out of the memory during the same clock cycle through a different port with the only common connection being the memory cells.

Apparatus for writing data to and reading data from a multi-port RAM in

A translinear static memory cell employs both bipolar and metal-oxide-semiconductor technologies. Bipolar transistors are employed as switching devices, whereas MOS transistors provide power supply and coupling functions. Among other advantages, the bipolar transistors provide large changes in output current for small changes in input voltage, thereby enabling high level read signals to be obtained. The MOS load and coupling transistors facilitate bidirectional current flow into and out of the cell, thereby enabling write operations to be achieved during relatively short periods of time.

Translinear static memory cell with bipolar and MOS devices

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Los Altos, CA, United States of America

Raymond A Heald