Via Technologies, Inc.

Ip-first, LLC

Raymond A Bertram

James R Lundberg

Darius D Gaskins

Vanessa Canac

Imran Qureshi

Matthew Russell Nixon

Mark J Brazell

Rochelle L Stortz

Mir Azam

Jim Lundberg

Elizabeth Longwell

A system for fast determination of a horizontal minimum of multiple digital values including a difference circuit and a compare circuit. The difference circuit may include first and second adders in which the first adder compares upper bits of a first digital value with upper bits of a second digital value and provides a first carry output and a propagate output. The second adder compares lower bits of the first digital value with lower bits of the second digital value and provides a second carry output. The compare circuit determines whether the first digital value is greater than the second digital value based on the carry and propagate outputs. Multiple difference circuits may be used to compare each of multiple digital values with every other digital value to provide corresponding compare bits, which are then used to determine a minimum one of the digital values and its corresponding location.

System and method for determination of a horizontal minimum of digital values

A system which uses common adder circuitry to perform either one of a horizontal minimum instruction and a sum of absolute differences instruction including multiple adders, a sum circuit, a compare circuit, and a routing circuit. The input operands include multiple digital values which are delivered by the routing circuit to the adders depending upon which instruction is indicated. Each adder determines a difference between a pair of digital values. The differences are grouped and summed together by the sum circuit for the sum of absolute differences instruction. The adders are paired together for the horizontal minimum instruction, in which each pair provides carry and propagate outputs. The upper portions of a pair of digital values are compared by the upper adder and the lower portions are compared by the lower adder, and the carry and propagate outputs are collectively used to determine the minimum value.

System and method of using common adder circuitry for both a horizontal minimum instruction and a sum of absolute differences instruction

A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail.

Microprocessor with selective substrate biasing for clock-gated functional blocks

A microprocessor including a substrate bias rail providing a bias voltage during a first operating mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes.

Microprocessor with substrate bias clamps

A bus inversion apparatus includes exclusive-OR gates and an inversion detector. The exclusive-OR gates are coupled to an instant data bus and a last data bus. The data buses have a corresponding plurality of bits, where the exclusive-OR gates perform a bitwise comparison of the data buses, and provide an exclusive-OR bus. The states of the exclusive-OR bus indicate whether corresponding bits of the data buses are different. The inversion detector counts the number of the corresponding bits that are different, and indicates that the instant data bus should be inverted. The inversion detector has a plurality of left shift circuits, each configured to perform a logical left shift of input bits as directed by the states of shift bits, where outputs of the each of the plurality of left shift circuits indicate a number of a subgroup of the corresponding bits that are different.

Data bus inversion detection mechanism

An N-domino latch includes a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal. The domino stage evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node high when the approximately symmetric clock signal is low, and discharges the pre-charged node to a low state if the logic function evaluates when the approximately symmetric clock signal is high, and keeps the pre-charged node high if the logic function fails to evaluate when the approximately symmetric clock signal is high, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is high.

N-domino output latch

A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes low, and pulls a pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The mux pulls a feedback node high if the pre-discharged node goes high during the evaluation window, and pulls the feedback node low if the pre-discharged node is low during the evaluation window. The output stage is coupled to the pre-discharged node and the feedback node. The output stage provides an output signal based on states of the pre-discharged and the feedback nodes.

Accelerated P-channel dynamic register

Dynamic logic register including evaluation logic, delay logic, latching logic, and a keeper circuit. The evaluation logic evaluates a logic function based on data input. The logic function evaluates to either a first state or a second state. The delay logic generates a kill signal, where the kill signal is a delayed version of a clock signal, and where the delay between the clock and kill signals comprises a hold time, and where the hold time is shortened when the logic function evaluates to the first state. The latching logic is responsive to the clock and kill signals and the state of pre-charged node, and controls the state of an output node based on the state of a pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of the kill signal, and otherwise presents a tri-state condition to said output node.

Inverting dynamic register with data-dependent hold time reduction mechanism

A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes high, and pulls a pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The mux pulls a feedback node low if the pre-charged node goes low during the evaluation window, and pulls the feedback node high if the pre-charged node is high during the evaluation window. The output stage is coupled to the pre-charged node and the feedback node. The output stage provides an output signal based on states of the pre-charged and the feedback nodes.

Accelerated N-channel dynamic register

A P-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-discharges a pre-discharged node low when the symmetric clock signal is high and opens an evaluation window when the pulsed clock signal goes low, and pulls the pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The output stage provides an output signal based on states of the pre-discharged node and a second preliminary output node.

P-domino register with accelerated non-charge path

An N-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-charges a pre-charged node high when the symmetric clock signal is low and opens an evaluation window when the pulsed clock signal goes high, and pulls the pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The output stage provides an output signal based on states of the pre-charged node and a second preliminary output node.

N-domino register with accelerated non-discharge path

A non-inverting domino register including a domino stage, a storage stage, a keeper circuit and an output stage. The domino stage includes evaluation logic, coupled between evaluation devices at a pre-charged node, which evaluates a logic function. The storage stage drives a first preliminary output node and includes a pull-up device and a pull-down device both responsive to the pre-charged node, and a second pull-down device responsive to the clock signal. The keeper circuit is a cross-coupled pair of inverters coupled between the first preliminary output node and a second preliminary output node. The output stage includes a pair of pull-up and pull-down devices for driving an output node. The first pull-up device and the first pull-down device are both responsive to the pre-charged node, and the second pull-up device and the second pull-down device are both responsive to the second preliminary output node.

Non-inverting domino register

A domino register including an evaluation circuit, a write circuit, an inverter, a keeper circuit, and output logic. The evaluation circuit pre-charges a first node and evaluates a logic function for controlling a state of the first node when the clock signal goes high. The write circuit drives a second node high if the first node is low and drives the second node low if the first node stays high during evaluation. The inverter inverts the second node to control the state of a third node. The keeper circuit keeps the second node high while the third node and clock signals are both low and keeps the second node low while the third and first nodes are both high. The high and low paths of the keeper circuit are otherwise disabled, including when the write circuit changes state. Thus, the write circuit does not have to overcome a keeper device.

A P-domino latch includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal, and evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node low when the approximately symmetric clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the approximately symmetric clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the approximately symmetric clock signal is low, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is low.

P-domino output latch

A P-domino register includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to a pulsed clock signal, and evaluates a logic function according to the states of at least one data signal and the pulsed clock signal, where the domino stage pre-charges a pre-charged node low when the pulsed clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the pulsed clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the pulsed clock signal is low, where a setup state of the at least one data signal is provided to the domino stage when the pulsed clock signal is high.

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Austin, TX, United States of America

Raymond A Bertram