Macronix International Co., Ltd.

Altera Corporation

Ray-Lin Wan

Chun-Hsiung Hung

Tzeng-Huei Shiau

I-Long Lee

Yu-Shen Lin

Yao-Wu Cheng

Kuen-Long Chang

Tom D Yiu

Fuchia Shone

Teruhiko Kamei

Yin-Shang Liu

Weitong Chuang

Kong-Mou Liou

Ken-Hui Chen

Han-Sung Chen

Tien-Ler Lin

Chun Hsiung Hung

Han Sung Chen

Ting-Chung Hu

Yu Shen Lin

Yuan-Chang Liu

Tien-Shin Ho

Yu-Sui Lee

Jun Takahashi

Wen-Pin Lu

Chia-Shing Chen

Fu-Chia Shone

Yu-Ming Hsu

Chuan-Yung Hung

Chung-Hsiung Hung

Tso-Ming Chang

Kouta Soejima

Kota Soejima

Kong Mou Liou

Chia Shing Chen

Hun-Song Chen

Tzing-Huei Shiau

Tzeng-Hei Shiau

Y T Lin

A four-phase charge pump circuit suitable for use on integrated circuits, such as flash memory devices, includes circuitry that drives charge pump nodes in two components separated by a time delay. The two components can be triggered by edges from the clocks that control the timing of the charge pump. Driving the charge pump nodes in two components separated by a delay decreases the peak current of the charge pump and improves noise characteristics of a voltage supply or ground line connected to the charge pump.

Four-phase charge pump with lower peak current

A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines. The defective bit lines in the first memory array can be disabled during the soft program and replaced by corresponding redundant bit lines disposed in the second memory array, so that the soft program is not applied to the defective bit lines. By preventing application of the soft program to the defective bit lines, the BLISP method avoids consumption of excessive current that would otherwise be consumed by very low threshold voltage memory cells disposed on the defective bit lines. The excessive current would render the soft program method much less efficient.

Method and integrated circuit for bit line soft programming (BLISP)

An improved word line boost circuit suitable for use on integrated circuits such as flash memory devices includes a two step boosting circuit with a floating circuit node. A first circuit provides an initial boost of the output voltage from a precharged voltage. Part of the first circuit is floated, lessening a load on a second circuit. Then, the second circuit provides a second boost of the output voltage with increased power efficiency. A time delay separates the onset of the second boosting operation from the onset of the first boosting operation so as to define a two-step boost.

Word line boost circuit

A method increases endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance. The method is based on arranging the array into a plurality of sectors, and assigning a subset of addresses for storage of data structure expected to change a number of times that is sufficient to exceed the specified endurance of the memory cell in the array. A record is maintained indicating one of the plurality of sectors as a current sector, directing accesses using the subset of addresses to the current sector, counting changes executed to memory cells identified by the subset of addresses for the current sector, and changing the current sector to another one of the plurality of sectors when the count of changes exceeds the threshold.

Technique for increasing endurance of integrated circuit memory

A triple well charge pump comprises a first transistor connected in a diode configuration having a first channel terminal, nominally the source, coupled to a first node, and the second channel terminal, nominally the drain, coupled to its gate and to a second node. A first capacitor has a first terminal coupled to the first node of the charge pump, and a second terminal adapted to receive a first clock signal. A second transistor has a first channel terminal coupled to the second node of the charge pump, and a second channel terminal coupled to its gate and to a third node. A second capacitor has a first terminal coupled to the second node, and a second terminal adapted to receive a second clock signal. The first and second transistors comprise a first region and a second region having a first conductivity type providing the first and second channel terminals respectively, a channel region in which the first and second regions are formed having a second conductivity type, and an isolation well having the first conductivity type in a semiconductor substrate. The first and second regions, the channel region and the isolation well form a parasitic bipolar junction transistor that has a threshold voltage. The channel region has a doping concentration establishing a threshold voltage for the MOS transistor which is less than the threshold voltage of the parasitic bipolar junction transistor. The clock signals have sloped rising and falling edges.

Low threshold MOS two phase negative charge pump

An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit. The detection circuit signals the voltage boost circuit when the node reaches the first threshold, and signals the voltage boost circuit when the node reaches the second threshold. According to one aspect of the invention, the first threshold is reached within less than 5 nanoseconds, and more preferably about 2 nanoseconds, or less, of the transition in the boost signal.

Rapid on chip voltage generation for low power integrated circuits

A circuit is provided for applying a negative voltage to the control gate of a floating gate memory cell and a positive voltage to the source drain or channel which comprises a positive voltage source to provide a positive voltage to the source of the cell, and a negative voltage source responsive to the supply voltage to provide a negative voltage to the control gate. A voltage regulator is included that is coupled to the negative voltage source and to the positive voltage source to maintain the negative voltage at a level responsive to the source voltage. The regulator maintains the negative voltage in response to the source voltage so that the electric field remains essentially constant over a range of values of source voltage.

Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices

A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.

Memory cell sense amplifier

A page mode flash memory or floating gate memory device, including a page buffer based upon low current bit latches, and additional capabilities for parallel read and parallel program verify operations. The present device includes bit latch circuitry and/or method steps that facilitate such parallel operations and avoid data conflicts. Circuitry for separate read signals can serve to isolate the operations. Additionally, circuitry tied to the data verification signal can also be used. A diode type device can be used to isolate signal conditions that might indicate the cell does not need to be programmed. Bit-by-bit precharging of the bit lines can also be employed in order to save precharging power. Additionally, the large capacitance of the dataline might be used to delay discharging a particular dataline, and thereby allow a latch enabling signal to go high, thus eliminating the need for further isolation circuitry, or the like.

Parallel read and verify for floating gate memory device

Enhanced word line driver to reduce gate capacitance for low voltage

Triple well charge pump

Automatic test process with non-volatile result table store

Power on reset circuit

Series capacitor charge pump with dynamic biasing

A method for determining successful programming of a set of memory cells in an array of floating gate memory cells including bit lines coupled with corresponding columns of cells in the array, word lines coupled with corresponding rows of cells in the array, and bit latches coupled to the respective bit lines. The method includes applying a word line voltage to a word line across which memory cells in the set of memory cells are accessible. A potential applied to memory cells in the set of memory cells is raised. A current load is caused from the bit line. Changes in respective voltage levels of bit lines in the set of bit lines are responded to in parallel to store a constant in bit latches in the set of bit latches coupled to bit lines on which the respective voltage levels pass a determinate threshold during the step of applying a word line voltage. An integrated circuit memory is described. The memory includes a device, connected to a bit line and ground, for selectively causing a current flow from the bit line at least before loading a constant into the memory element.

Bit latch scheme for parallel program verify in floating gate memory

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Fremont, CA, United States of America

Ray-Lin Wan