Macronix International Co., Ltd.

Other

Ray L Wan

Tien-Ler Lin

Tom D Yiu

Fuchia Shone

Ling-Wen Hsiao

Han-Sung Chen

Chun Hsiung Hung

Tzeng-Huei Shiau

Kong-Mou Liou

Gilbert Sung

Chun-Hsiung Hung

Kuen-Long Chang

Yu-Shen Lin

I-Long Lee

Han Sung Chen

Kuo Yu Liao

Yuan-Chang Liu

Jin-Lien Lin

Tien-Shin Ho

Tso-Ming Chang

Chung-Cheng Tsai

An output driver for an integrated circuit performs a precharge function before internal data is available, minimizing the access time for such data. Also, the pull up and pull down circuitry used in the precharge function is separate from the output driver, and independent of the level of the data signal to be driven. A sense circuit senses an initial state of the output pad, before the output signal is supplied to the output pad, which indicates whether a voltage level on the output pad is above a threshold or below the threshold. A precharge circuit includes a pull up circuit and a pull down circuit. The pull up circuit is responsive to the initial state indicating that the voltage level on the output is below the threshold, and the pull down circuit is responsive to the initial state indicating that the voltage level on the output is above the threshold. A detector is coupled to the output, and produces a control signal indicating when output is near the threshold. Logic is responsive to the control signal from the detector to turn off the precharge circuit when the threshold is reached.

Output pad precharge circuit for semiconductor devices

A non-volatile integrated circuit memory, such as a flash memory device based on floating gate transistor memory cells, with read while write capability is provided using a single address register. The integrated circuit includes at least two independent arrays of memory cells. During a program or an erase operation in one array on the non-volatile integrated circuit, a read operation can be executed in the other array on the same integrated circuit by bypassing the address register altogether, and allowing the register to remain in use by the program or erase operation. A bypass combinatorial logic path for the read process is coupled to the same address inputs as the address register, and operable in parallel with the registered address path.

Non-volatile integrated circuit having read while write capability using one address register

A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

Fast flash EPROM programming and pre-programming circuit design

The present invention provides a new memory device for storage of boot code for microprocessors which boot to either the top or bottom of a memory map on power-up. The device includes a memory array, a first block, and decoders. The first block is defined as rows of the memory array designated for storage of data. The decoders decode a memory access requested for the data. The memory access request may be in either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array, a decoder, a control, and a logic gate. The decoders decode a memory access request to select a row of memory array. The control has an output for outputting either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical 'Exclusive Or' of the control signal and a corresponding bit of the memory access request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.

Memory supporting multiple address protocols

An integrated circuit comprises a functional module such as a FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port is provided on the integrated circuit coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile status write circuitry, is coupled to the program and erase circuitry and the test set, and writes the status information to the test set. The program and erase circuits include retry counts with programmable thresholds for reducing the test times of the devices.

Automatic test circuitry with non-volatile status write

A system for programming arrays of floating gate memory cells reduces programming current requirements, and reduces wordline and bitline stress during programming. A word-to-be-programmed into a floating gate memory array is divided into a plurality of smaller subwords. Only one subword is programmed at a time, thereby reducing programming current requirements. Additionally, subwords which are successfully programmed are not reprogrammed even if bits in other subwords do not program properly. This creates less wordline stress than previous systems which program an entire word at once, thereby requiring subwords which program successfully to be reprogrammed along with subwords which fail to program. Finally, within each subword only those bits which failed to program are reprogrammed, thereby reducing bitline stress during reprogramming for those bits which were successfully programmed.

Low current floating gate programming with bit-by-bit verification

An integrated circuit (IC) includes a functional module such as FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port on the integrated circuit is coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells, a test set of FLASH EPROM memory cells, and a port through which data in the array is accessible by external devices. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile status write circuitry is coupled to the program and erase circuitry and the test set, and writes the status information to the test set. The program and erase circuits include retry counts with programmable thresholds for reducing the test times of the devices.

A FLASH EPROM device includes a memory array organized into a plurality of blocks of memory cells. An energizing circuit applies energizing voltages to the blocks of memory cells to read and program addressed cells, and to erase selected blocks or the whole memory array. An erase verify circuit separately verifies erasure of blocks in the plurality of block memory cells. Control logic controls the energizing circuit to re-erase blocks which fail erase verify. The control logic includes a plurality of block erase flags which correspond to respective blocks of memory cells in the array. The erase verify is responsive to the block erase flags to verify only those blocks having a set block erase flag. If the block passes erase verify, then the block erase flag is reset. Only those blocks having a set block erase flag after the erase verify operation are re-erased. To support this operation, the circuit also includes the capability of erasing only a block of the memory array at a time.

Flash EPROM with block erase flags for over-erase protection

Fast FLASH EPROM programming and pre-programming circuit design

Fast pre-programming circuit for floating gate memory

Flash EPROM integrated circuit architecture

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Milpitas, CA, United States of America

Ray L Wan