Microchip Technology Inc.

Other

Ray L Allen

Rodney J Drake

Ajay J Padgaonkar

Eric Berman

Randy L Yach

Sumit K Mitra

Tom Salt

Martin Burghardt

Greg Italiano

N Cole Harrison

A single semiconductor chip device is utilized for controlling an external system which has a liquid crystal display (LCD) associated therewith. A dual port random access memory (RAM) stores data representative of information to be displayed on the LCD. The RAM includes a plurality of master data storage latches and a single slave data storage latch shared by all of the plurality of master storage latches. A microcontroller has a central processing unit (CPU) for communicating with the master storage latches via one of the RAM ports to periodically change the data stored therein. An LCD control module successively updates the data in the single slave storage latch with data from each of the master storage latches and downloads the updated data from the single slave storage latch to a temporary store associated with the LCD after each update from a master storage latch and before the update of data from the next master storage latch. Consequently, data in each master storage latch may be changed periodically by the CPU without interference with downloading of updated data from the single slave storage unit.

Microcontroller with dual port ram for LCD display and sharing of slave

A RISC-based microcontroller is described which uses 'split' data buses in the functional areas of the ALU and the I/O peripheral control interface. Also, the 'Harvard' architecture is applied with separate buses for instructions and operational data which are stored and supplied from separate memories, i.e., an instruction memory and a data memory. This architecture allows to run the microcontroller with timing and clocking schemes of higher frequencies resulting in faster speed and higher processing rates in MIPS. The different functional components of the microcontroller can be placed on a single VLSI chip while other designs with much less on-chip functions are also conceivable.

RISC-based microcontroller with peripheral function added to a split

A microcontroller and associated EPROM program memory are fabricated in a single semiconductor chip. The microcontroller device is adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in circuit with a system to be controlled by the device, and to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. The in-circuit programming uses considerably less than the total number of input/output (I/O) pins of the device, which in total are fewer than the number of bits in a command word. This is achieved with a serial/parallel programming interface between the pins and the program memory, and by applying the data in serial fashion to the interface where it is latched and loaded in parallel in the memory. Input data to the device may alternatively be entered in parallel to the interface in bytes of width less than the total number of I/O pins of the device.

System having input output pins shifting between programming mode and

A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory with programmable EPROM configuration fuses located in a limited number of addresses of the on-chip program memory, the condition of each of EPROM fuse being defined as blown or not blown according to the value of the bit stored in the respective address of the on-chip program memory. The operating modes of the microcontroller are configurable by appropriately programming at least some of the EPROM fuses. Testing of the microcontroller in at least some of the operating modes is achieved by using latches outside the program memory to emulate the EPROM fuses, while suppressing the capability to set the condition of the EPROM fuses during the testing. Upon completion of the testing, control of the operating modes of the microcontroller is returned to the EPROM fuses, and the latches are precluded from further emulating the EPROM fuses.

Microcontroller with fuse-emulating latches

A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory. The microcontroller is selectively configurable to operate in any one of a plurality of predetermined operating modes, including at least one secure microcontroller mode. A plurality of EPROM configuration fuses used for configuring the microcontroller and protecting its program memory from read, verify or write through any instruction initiated from other than a predetermined secure area of the chip, are mapped into the on-chip EPROM program memory as bits in respective address locations thereof. The value of a bit representing any one of said fuses is effective to determine the condition of the respective fuse. That condition is observed by reading the value of the respective bit for that fuse stored in the EPROM program memory. The chip security is enabled by configuring the microcontroller in a code protected mode by programming the bits representing the desired fuses in the EPROM program memory to effectively blow or erase each fuse according to the desired configuration.

System and method for protecting contents of microcontroller memory by

A single chip, semiconductor microcontroller device is adapted to control an aspect of the operation of an external system. The device includes a CPU, program memory for storing instructions to be selectively executed by the CPU to perform the control functions, and peripheral EEPROM data memory adapted to be written to for storing selected data in selected ones of a multiplicity of addresses of the data memory and for selective retrieval of the stored dam by the CPU within its control function. Internal logic in the device is implemented to abort a write operation in progress on the EEPROM data memory upon occurrence of an asynchronous reset of the device. An error flag is set by the logic to indicate that the write operation is being aborted, and the data that was partially written to the EEPROM memory at the time the write operation was aborted is held intact.

Premature termination of microcontroller EEPROM write

An electrostatic enhancement apparatus for a video arcade or other game, including an electrostatic generator for generating a high voltage low current electrostatic charge, an electrode coupled to the generator for providing the electrostatic charge to a player, and control circuitry responsive to a control signal from the game for actuating the electrostatic generator to provide the electrostatic charge to the player upon the occurrence of a predetermined event in the game. The preferred embodiment includes an isolation booth for surrounding and electrically isolating the player during the electrostatic charging and preventing accidental discharge. Also included is a discharge arm mounted for electrical engagement with the electrode for removing charge from the electrode and the player under certain circumstances.

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Atlanta, GA, United States of America

Ray L Allen