Vlsi Technology, Inc.

Ray Killorn

Dexin Liang

A digital phase shift amplification and detection system and method. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect timing delays in the amplified signal. In one embodiment, the present invention relates to a digital phase shift amplification and detection system and method. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect the amplified timing differences in the amplified signal as a result of a relatively smaller timing change in an input signal. The detection circuit is coupled to clock signals that are out of phase with the clock signal that triggers the metastable flip flop in the phase shift amplifier. The amount of phase shift between the clock signals impacts the position of nominal times in the metastable region. In addition, the greater the number of flip flops in the detection circuit that are coupled to clock signals that trigger the flip flop at a different time from any other flip flop in the detection unit, the greater the ability to differentiate and proportional sensitivity the present embodiment has to small timing differences in an input signal.

Digital phase shift amplification and detection system and method

A digital phase shift amplification and detection system and method for amplifying and detecting a phase shift. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region in which the applied signal transitions at a relatively close time to a trigger in the clock signal of the flip flop. The digital phase shift amplification and detection system and method amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect timing delays in the amplified signal. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect the amplified timing differences in the amplified signal as a result of a relatively smaller timing change in an input signal. The detection circuit is coupled to clock signals that are out of phase with the clock signal that triggers the metastable flip flop in the phase shift amplifier. The amount of phase shift between the clock signals impacts the position of nominal times in the metastable region. In addition, the greater the number of flip flops in the detection circuit that are coupled to clock signals that trigger the flip flop at a different time from any other flip flop in the detection unit, the greater the ability to differentiate and proportional sensitivity the present embodiment has to small timing differences in an input signal.

A flat, thin decoupling capacitor is disposed inside an integrated circuit device in a coplanar relationship with a semiconductor chip and a bonding element. When connected to the power and ground plane of a device substrate or in a leadframe device, the decoupling capacitor is positioned close to the semiconductor chip to substantially reduce ground bounce and crosstalk from the semiconductor chip. When the decoupling capacitor is positioned to locate the semiconductor chip between itself and the device substrate or leadframe device, the decoupling capacitor shields electromagnetic interference from the semiconductor chip.

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San Jose, CA, United States of America

Ray Killorn