Taiwan Semiconductor Manufacturing Comp. Ltd.

Ray Chuang

Jung-Chih Tsao

Steven Lin

Chi-Wen Liu

Hsi-Kuei Cheng

Ming-Yuan Cheng

Hsien-Ping Feng

Kei-Wei Chen

Chih-Tsung Lee

Shih-Chi Lin

Chi-Ching Lo

Cheng-Liang Chang

Huan-Wen Lai

Shien-Ping Feng

Jen Wei

Chian-Kuo Huang

Ching-Sun Lee

Cheng-Yua Chuang

Neo-Feng Chiou

Yen-Bo Huang

Chi-Wen Li

Jye-Wei Hsu

Hsien-Pin Fong

An apparatus and method for preventing the peeling of electroplated metal from a wafer, is disclosed. The apparatus includes a seed layer detector system having a light source and a reflectivity detector. According to the method, the light source emits a beam of light onto a wafer and the reflectivity detector receives the light reflected from the wafer. The reflectivity of the wafer surface is measured to determine the presence or absence of a seed layer on the wafer, as well as whether the seed layer has a minimum thickness for optimum electroplating of a metal onto the seed layer.

Apparatus and method for preventing copper peeling in ECP

A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cmcurrent density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a Hplasma treatment. A second ECP process with a first deposition step at a 40 mA/cmcurrent density and second deposition step at a 60 mA/cmcurrent density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

[object Object]

A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness tis formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness twhere t&#x2266;tand having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (G)&#x2267;Gfor the second copper layer.

Method to reduce Rs pattern dependence effect

A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

Method of reducing the pattern effect in the CMP process

A disassembling device for separating a pedestal, a ceramic element and a base from an electrostatic chuck assembly. The base has a first end surface and a second end surface. The ceramic element is disposed on the first end surface. The pedestal is disposed on the ceramic element. The disassembling device includes a main body and at least one pushing element. The main body is disposed on the second end surface and has a through hole. The at least one pushing element penetrates the through hole and pushes against the ceramic element and pedestal to separate the ceramic element and pedestal from the first end surface of the base.

Electrostatic chuck assembly having disassembling device

A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cmcurrent density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a Hplasma treatment. A second ECP process with a first deposition step at a 40 mA/cmcurrent density and second deposition step at a 60 mA/cmcurrent density is used to deposit a second copper layer-that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

Post ECP multi-step anneal/H2 treatment to reduce film impurity

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Taipei, Taiwan

Ray Chuang