Motorola Corporation

Freescale Semiconductor,inc.

Vlsi Technology, Inc.

Ray Chang

Stephen T Flannagan

Kenneth W Jones

William R Weier

Lawrence F Childs

Karl L Wang

Richard Y Wong

Glenn E Starnes

Donovan L Raatz

Ruey J Yu

Mark D Bader

Richard Wong

William Weier

A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.

Programmable delay control for sense amplifiers in a memory

Fuses and detect circuits (124) in an integrated circuit memory (100) include a copper fuse (208) and a fuse state detect stage (202) for detecting the open circuit state or the closed circuit state of the fuse (208). The fuse detect circuit (124) provides an output signal corresponding to the state of the fuse and during detecting, limits a voltage drop across the fuse to an absolute value independent of a power supply voltage applied to the integrated circuit memory. The fuse detect circuit (124) operates at power up of the integrated circuit memory (100) and is disabled after the state of the fuse is detected and latched, and the power supply is sufficient for reliable operation of the integrated circuit memory (100). By limiting the voltage drop across a blown copper fuse (208), a potential electro-migration problem is reduced.

Integrated circuit memory having a fuse detect circuit and method

A memory utilizing programmable delay circuits to control address buffers. A programmable delay device is provided for each block of a plurality of blocks of the memory device. Each block is associated with a corresponding bit array for storing data for the associated block. The delay device is used to delay activation of sense amplifiers from the time the block is selected which, in turn, corresponds to the duration of the addresses that are provided to the bit array within the block. Each of the delays within each block is programmed by a global fuse circuit, so that all of the blocks are programmed with the same delay. After fabrication of the memory device onto an integrated circuit (IC), all of the data paths within each block are measured under various voltage and temperature conditions to identify the slowest data path of all blocks of the memory device. Once a particular delay is identified for the slowest data path within the memory device, all of the programmable delays within each block are programmed with a corresponding delay. In this manner, all of the sense amplifiers within any selected blocks are activated after the programmed delay to ensure valid data. A similar delay device is provided within the clock control circuitry to pulse-width control the clock signal provided to the address buffers. The global fuse circuit used to program the delay device within each of the blocks is also used to program the delay device within the clock control circuit so that the program delay within the clock control circuit and the data blocks are essentially the same.

Memory utilizing a programmable delay to control address buffers

A memory has a sense amplifier that provides data onto a global data line that is received by a secondary amplifier. The sense amplifier is precharged to a high voltage and responds to data provided by a selected memory cell on a pair of bit lines. The amplifier is a dynamic amplifier that latches the data but also limits the output voltage swing provided to the secondary amplifier. By limiting the voltage swing on the high-capacitance global data lines, there is significant power savings. The voltage swing that is provided is sufficient for reliable detection by the secondary amplifier.

Dynamic sense amplifier in a memory capable of limiting the voltage

A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers that are coupled to the same global data lines are enabled by clocks that are timed by a common clock signal. The memory has subarrays in which each subarray is divided into blocks. When a block is selected, a corresponding block select signal is generated. The sense amplifiers and the secondary amplifiers that are coupled in common with the enabled sense amplifiers in the selected block are enabled in response to this block select signal. The block select signal that enables the sense amplifiers initiates a secondary amp control signal which, after a programmed delay, enables the secondary amplifier.

Timing control of amplifiers in a memory

A layout portion (20) has a first portion (25), and a second portion (55). In the first portion (25), a reference voltage line (27) is disposed between two V.sub.DD power supply lines (26, 30) for a first predetermined length, for providing capacitive coupling between V.sub.DD and a reference voltage. In the second portion (55), the reference voltage line (27) is disposed between two V.sub.SS power supply lines (28, 41) for a second predetermined length, for providing capacitive coupling between V.sub.SS and the reference voltage. The capacitive coupling stabilizes the reference voltage with respect to the power supply voltage, and reduces power supply noise due to lead inductance and changing current demand. In addition, the power supply lines (26, 28, 30, 41) are disposed half above an N-type region (22) and half above a P-type substrate (21) for reducing local transistor switching noise.

Layout for noise reduction on a reference voltage

A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

Delay locked loop for detecting the phase difference of two signals

A power-on reset circuit (30) for a memory (20) includes a DC model circuit (39), an N.sub.BIAS check circuit (64), and a NAND logic gate (71). A logic low power-on reset signal is provided at power-up of the memory (20) to establish initial conditions in a clock circuit (29) and in row and column predecoders/latches (24, 27). When the power supply voltage, a bandgap reference voltage, and a bias voltage all reach their predetermined voltages, the power-on reset circuit (30) provides a logic high power-on reset signal. In this manner, the power-on reset circuit (30) is assured of providing a logic low power-on reset signal until all of the proper voltage levels are reached. In addition, the power-on reset circuit models a DC circuit equivalent of an address buffer circuit (79) for compensating for process and temperature variations.

Power-on reset circuit for preventing multiple word line selections

A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). The arbiter circuit (264) compares a clock signal to a delayed clock signal from the VCD circuit (260). In response, the arbiter circuit (264) provides a retard signal to the VCD control circuit (265). The VCD control circuit (265) receives the retard signal and adjusts a propagation delay of the delayed clock signal to compensate for changes in the clock frequency, as well as to compensate for process, temperature, and power supply variations.

Write control for a memory using a delay locked loop

An ECL-to-CMOS buffer having a single-sided delay comprises an ECL logic gate, a level converter, a plurality of series connected inverters, and a NOR gate. The ECL logic gate receives an ECL level input signal, and provides complementary intermediate level logic signals. The level converter receives the intermediate level logic signals and provides a CMOS level output signal. The NOR gate receives the CMOS level output signal, via the series connected inverters, at an input terminal after a predetermined delay. One of the intermediate level logic signals is also received by the NOR gate at a second input terminal. The CMOS level output signal is delayed for a predetermined time in a low-to-high transition, with no unwanted delay in a high-to-low transition.

ECL-to-CMOS buffer having a single-sided delay

A pipelined memory (20) has a synchronous operating mode and an asynchronous operating mode. The memory (20) includes output registers (34) and output enable registers (48) which are used to electrically switch between the asynchronous operating mode and the synchronous operating mode. In addition, in the synchronous operating mode, the depth of pipelining can be changed between a three stage pipeline and a two stage pipeline. By changing the depth of pipelining, the memory (20) can operate using a greater range of clock frequencies. In addition, the operating frequency can be changed to facilitate testing and debugging of the memory (20).

Pipelined memory having synchronous and asynchronous operating modes

A memory (20) for performing read cycles and write cycles has memory cells (30) located at intersections of word lines (32) and bit line pairs (34). A write control circuit (44) receives a write enable signal. The logic state of the write enable signal determines whether memory (20) writes data into, or reads data from, memory (20). Memory (20) includes row address decoding for selecting a word line (32). During a write cycle, a control signal generated by write control circuit (44) and single-sided delay circuit (45) is provided to row predecoder (42). The old row address is latched, and a new address is prevented from selecting a new word line (32) until the write enable signal changes state to begin a read cycle. Controlling word line selection with the write enable signal ensures that bit line equalization occurs before the beginning of a read cycle.

Memory having a write enable controlled word line

A memory (20) has a read cycle and a write cycle. During the read cycle, differential data signals, corresponding to data provided by a selected memory cell, are superimposed on a first common mode voltage and provided to data output buffers (70-73). During the write cycle, differential data signals on read global data lines (61-62) are equalized at a second common mode voltage and data output buffers (70-73) are disabled. Output enable circuit (74) provides an output enable signal halfway between the first and second common mode voltages. Data output buffers (70-73) are enabled at the beginning of the read cycle when the differential data signals cross the output enable signal as they transition from the second common mode voltage to the first common mode voltage. Enabling data output buffers (70-73) in this way greatly relaxes output enable timing constraints.

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Ray Chang