Microsoft Technology Licensing, LLC

Ray Bittner

Darko Kirovski

Benjamin Zorn

Karthik Pattabiraman

Erik S Ruf

Steven Mark Drucker

Curtis Glenn Wong

Alessandro Forin

Michael Jack Sinclair

David William Voth

Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.

Block floating point for neural network implementations

Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Leveraging chip variability

A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.

Direct communication between GPU and FPGA components

One or more techniques and/or systems are provided for creating socially authored, or community authored, summaries of documents and/or for navigating a forum comprising such summaries. In one embodiment, at least some of the summaries are generated automatically when a document is written and/or discovered (e.g., by a web crawler), for example. In another embodiment, the documents are created by users of the forum. A plurality of summaries of a document may be created (e.g., by different users), and users can provide feedback, such as comments or ratings, that may assist other users in identifying which summary or summaries better describe the document. Moreover, the users can navigate the forum and retrieve summaries by browsing categories (and subcategories) to identify a topic of interest and/or by performing a search based upon user inputted search term(s).

Community authoring content generation and navigation

An input device includes an array of adjacent capacitive sensors arranged into rows and columns. Each capacitive sensor exhibits a capacitance characteristic when in proximity to a conductive element. A plurality of mechanical hysteresis mechanisms are each deposited on and in contact with each of the capacitive sensors and configured to be actuated by a corresponding push button. Each capacitive sensor exhibits an electrical characteristic upon actuation of the corresponding mechanical hysteresis mechanism. An insulating overlay layer positioned over the array of capacitive sensors and the plurality of mechanical hysteresis mechanisms defines each push button and defines a surface for accommodating the conductive element.

Pointing and data entry input device

A content addressable memory (CAM) architecture comprises two components, a small, fast on-chip cache memory that stores data that is likely needed in the immediate future, and an off-chip main memory in normal RAM. The CAM allows data to be stored with an associated tag that is of any size and identifies the data. Via tags, waves of data are launched into a machine's computational hardware and re-associated with related tags upon return. Tags may be generated so that related data values have adjacent storage locations, facilitating fast retrieval. Typically, the CAM emits only complete operand sets. By using tags to identify unique operand sets, computations can be allowed to proceed out of order, and be recollected later for further processing. This allows greater computational speed via multiple parallel processing units that compute large sets of operand sets, or by opportunistically fetching and executing operand sets as they become available.

Growing community of inventors

Sammamish, WA, United States of America

Ray Bittner