Microsoft Technology Licensing, LLC

Microsoft Corporation

Ray A Bittner, Jr

Michael Ginsberg

Kenneth Hiroshi Eguro

Michael Jack Sinclair

Lin Zhong

David William Voth

Alessandro Forin

Frank Torsten Bernd Seide

Shawn Michael Swilley

George E Smith

Rehan Ahmed

Ji Sun

David W Voth

In a data center, neural network evaluations can be included for services involving image or speech recognition by using a field programmable gate array (FPGA) or other parallel processor. The memory bandwidth limitations of providing weighted data sets from an external memory to the FPGA (or other parallel processor) can be managed by queuing up input data from the plurality of cores executing the services at the FPGA (or other parallel processor) in batches of at least two feature vectors. The at least two feature vectors can be at least two observation vectors from a same data stream or from different data streams. The FPGA (or other parallel processor) can then act on the batch of data for each loading of the weighted datasets.

Memory bandwidth management for deep learning applications

The subject disclosure is directed towards loading parallel memories (e.g., in one or more FPGAs) with multidimensional data in an interleaved manner such that a multidimensional patch/window may be filled with corresponding data in a single parallel read of the memories. Depending on the position of the patch, the data may be rotated horizontally and/or vertically, for example, so that the data in each patch is consistently arranged in the patch regardless of from which memory each piece of data was read. Also described is leveraging dual ported memory for multiple line reads and/or loading one part of a buffer while reading from another.

Parallel memories for multidimensional data access

An intrusion detection system disclosed herein includes a detector circuit that measures a change in value of impedance of an interconnection circuitry. A decoder coupled to the detector decodes the measured value of the change in the impedance of the interconnection circuitry to determine existence of an abnormal condition. In an example implementation of the intrusion detection system, the change in the value of the impedance of the interconnection circuitry is represented by a change in the phase delay on the interconnection circuitry. An implementation of the intrusion detection circuit terminates communication using the interconnection circuitry upon detection of the abnormal condition. The intrusion detection system is further configured to interpret the abnormal condition as a communication signal to the interconnection circuitry.

Intrusion detection and communication

A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices. When application program threads require access to a PCI device, the operating system writes the high order bits of the PCI device address to two places: (1) the extension register of the PCI host bridge to allow immediate addressing of the PCI device, and (2) separate memory locations associated with the threads. When a context switch occurs from a first thread to a second thread, the operating system retrieves the stored value from the memory location associated with the second thread and writes the value to the extension register. In this manner, when the second thread requires access to its PCI device, the proper address value is already located in the extension register.

Dynamic address windowing on a PCI bus

A Random Access Memory (RAM) based Content Addressable Memory (CAM) architecture is disclosed. In an implementation, the CAM architecture includes a CAM data structure associated with a RAM to store one or more tags and associated data values. Each of the tags includes one or more bit fields which are utilized as an index for referencing a look-up table. One or more look-up tables may be realized for supporting memory operations facilitating efficient transfer modes available in the RAM.

Random Access Memory (RAM) based Content Addressable Memory (CAM) management

A mobile server is wirelessly communicable with at least one remote input/output (I/O) device to form a wireless personal-area network (PAN). The mobile server has at least one application program interface (API) allowing an application of arbitrary implementation on the mobile server to recognize and control at least one service implemented by the remote I/O device.

Interfacing I/O devices with a mobile server

A power regulating system and method are provided for regulating power in a portable computing device. The portable computing device includes microprocessing and radio communication capabilities. The power regulating system utilizes a number of power states to regulate the device's internal power source voltage. The power regulating system operates to selectively control and regulate the device's internal power consumption based on the power state of the device, and thereby extends the useful life of the device by prolonging the battery life of the device.

Power regulation system and method for a portable electronic device

A computer system includes a centerplane formed by a printed circuit board. The centerplane has a plurality of Desktop PCI electrical connectors on one side and a plurality of CompactPCI electrical connectors on the other. This allows the use of both Desktop and CompactPCI boards in a signal bus board, without requiring complex bridging circuits. In addition, this allows additional boards to be used without extending the length of the PCI bus.

PCI and compactpci integration

A PCI reflected-wave communications bus has a plurality of individual signal lines. Each signal line is terminated with a resistive-capacitive filter to partially dampen voltage wave reflections.

Growing community of inventors

Redmond, WA, United States of America

Ray A Bittner, Jr