Texas Instruments Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Sgs-thomson Microelectronics Limited

Stmicroelectronics Gmbh

Other

Ravishankar Sundaresan

Loi Ngoc Nguyen

Lap Chan

Shivaling S Mahant-Shetti

Cher Liang Cha

Satwinder S Malhi

Che-Chia Wei

Robert H Eklund

Mishel Matloubian

Gordon P Pollack

Mark G Harward

Hon W Lam

Wei Tony Chen

Lawrence A Arledge, Jr

Tony Wei Chen

A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

Sram cell fabrication with interlevel Dielectric planarization

A VLSI contact formation process in which a nitride layer is used to stop a wet oxide etch. An anisotropic plasma etch is used to cut a substantially vertical contact hole through the nitride and underlying layers. Thus, the resulting contact hole has a &ldquo;Y&rdquo;-shaped profile.

Method and interlevel dielectric structure for improved metal step coverage

An asymmetrical polysilicon thin film transistor is formed above a gate electrode on a semiconductor substrate. The transistor is separated from the gate electrode by a gate oxide layer, and includes a channel region immediately above the gate electrode. Highly doped source/drain regions are formed within the polysilicon on either side of the channel region. On the drain side of the channel only, a lightly doped drain region is formed between the channel region and the highly doped drain region. The highly doped source region is immediately adjacent the channel region.

Method of fabricating a one-sided polysilicon thin film transistor

A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions. The second electrode layer is etched through to form separate conductive connections. An intermetal dielectric layer is deposited. The intermetal dielectric layer is etched through to form contact openings. A metal layer is deposited and etched through to form separate metal interconnects. A passivation layer is deposited, and the integrated circuit is completed.

Method to form shallow junction transistors while eliminating shorts due to junction spiking

Shallow junction transistors which eliminating shorts due to junction spiking

A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.

Method of making a field effect transistor having a channel in an epitaxial silicon layer

A TFT formed on a semiconductor substrate of a first conductivity type, includes a first doped portion of a polysilicon layer over FOX regions and a first insulating layer. A buried contact extends through the first portion of a polysilicon layer and the first insulating layer to the surface of the substrate adjacent to a FOX region. A second doped portion of the polysilicon layer overlies the first portion and forms a buried contact between the second portion and the substrate. The polysilicon layer forms a gate electrode and a conductor from the buried contact. Doped source/drain regions in the substrate are juxtaposed with the gate electrode. An interelectrode dielectric layer over the gate electrode and the conductor has a gate opening therethrough down to the substrate. A gate oxide layer is formed on the surface of the substrate at the gate opening. A semiconductor film extends over the interelectrode dielectric layer and over the surface of the substrate through the gate opening. A doped channel region is formed between source/drain regions in the semiconductor film above the gate opening, and above the gate opening of a TFT, with the doped region therebelow comprising the gate of the TFT.

SRAM cell with thin film transistor using two polysilicon layers

A semiconductor device comprises a semiconductor substrate of a first conductivity type with a first insulating layer formed on the semiconductor substrate and a thin film field effect transistor with a control gate containing a refractory metal silicide formed on the semiconductor substrate over the first insulating layer. A second insulating layer covers the control gate electrode. A semiconductor film is formed on the semiconductor substrate over the first and second insulating layers and having a first region of a second conductivity type opposite to the first conductivity type. A second region of the first conductivity type is formed in contact with a first end of the first region. A third region of the first conductivity type is formed in contact with a second end of the first region. The control gate electrode and a part of the first region are overlapped with each other over the second insulating layer. The second end of the first region is apart from the second side surface of the control gate electrode by a distance more than a thickness of a part of the second insulating layer covering a side surface of the control gate electrode and overlaps with the control gate electrode, wherein the second and third regions serve as a source and a drain of the thin film field effect transistor, respectively.

Thin film transistor with titanium nitride or refractory metal gate in

A JFET device is formed on a semiconductor body comprising an active region for the junction field effect device. A drain region layer is formed below the lower portion of the active region. The top surface of the body is doped to provide a source region layer on the device. Gate trenches extend through the source region layer forming source regions therein. The gate trenches also extend partially through the epitaxial layer. The gate trenches have sidewalls and bottoms. Dielectric spacer layers cover the sidewalls of the gate trenches upon surfaces of the source layer and the epitaxial layer in the gate trenches. Self-aligned gate regions are formed at the bottoms of the gate trenches in doped portions of the active region.

Self-aligned JFET

A device is disclosed which combines the advantages of CMOS and bipolar using an existing parasitic bipolar device. As such high on-chip density is attainable with the device along with high speed capability while maintaining low power advantages.

CMOS with parasitic bipolar transistor

A semiconductor device comprises a semiconductor substrate of a first conductivity type with a first insulating layer formed on the semiconductor substrate and a thin film field effect transistor with a control gate containing a refractory metal silicide formed on the semiconductor substrate over the first insulating layer. A second insulating layer covers the control gate electrode. A semiconductor film is formed on the semiconductor substrate over the first and second insulating layers and having a first region of a second conductivity type opposite to the first conductivity type. A second region of the first conductivity type is formed in contact with a first end of the first region. A third region of the first conductivity type is formed in contact with a second end of the first region. The control gate electrode and a part of the first region are overlapped with each other over the second insulating layer. The second end of the first region is apart from the second side surface of the control gate electrode by a distance more than a thickness of a part of the second insulating layer covering a side surface of the control gate electrode and does not overlap with the control gate electrode, wherein the second and third regions serve as a source and a drain of the thin film field effect transistor, respectively.

Growing community of inventors

Garland, TX, United States of America

Ravishankar Sundaresan