Texas Instruments Corporation

Raviprakash Suryanarayana Rao

Stephen Keith Heinrich-Barna

Srinivasa Raghavan Sridhara

Parvinder Kumar Rana

Vipul Kumar Singhal

Atul Ramakant Lele

Keshav Bhaktavatson Chintamani

Premkumar Seetharaman

Ajith Subramonia

Malav Shrikant Shah

Bharath Kumar Poluri

Sanjeev Kumar Suman

A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Memory circuit with leakage compensation

A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.

Automatic latch-up prevention in SRAM

An embodiment of the invention discloses a method for writing concurrently a binary logical value to one or more dummy memory cells in a dummy bit line pair. A diode is electrically connected between a power supply and the positive power supply line connected to the dummy memory cells. The binary logical value is then driven on to the dummy bit line pair. Next, one or more dummy word lines are driven to a logical high allowing selected dummy memory cells to be written with the binary logical value. After the selected dummy memory cells have been written to, the one or more dummy word lines are driven to a logical low. Next the diode is disabled by turning on a PFET connected between the power supply and the positive power supply line. Turning on the PFET also electrically connects the power supply to the positive power supply line.

Initializing dummy bits of an SRAM tracking circuit

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Allen, TX, United States of America

Raviprakash Suryanarayana Rao