Intel Corporation

Raviprakash Nagaraj

Leonard O Turner

Frank P Hart

Kenneth W Reese

Arthur L Spurrell

Ted L Boaz

Christopher S Moore

Krishnan Ravichandran

Gurbir Singh

Xia Dai

Cau L Nguyen

Edwin J Pole, Ii

John T Orton

James L Fafrak

Leonard Goodell

Reinhard Stotzer

Technologies for split key security include a payment device to generate a key encryption key and a first key encryption key part. The payment device generates a second key encryption key part based on the key encryption key and the first key encryption key part and deletes the key encryption key in response to generating the second key encryption key part. Further, the payment device stores the first key encryption key part to a secure memory of a security co-processor of the payment device and the second key encryption key part to a secure memory of a secondary processor of the payment device. The secondary processor is electrically coupled to a backup energy source.

Technologies for split key security

Systems, methods, and devices are directed to an electronic device that includes a first wireless communication module configured to facilitate transmission and reception of data via a wireless communication link and a first secure element while a wireless communication device includes a processor, an operating system executed by the processor, a second wireless communication module configured to facilitate transmission and reception of data via the wireless communication link, and a second secure element. The second secure element exchanges information with the first secure element via the wireless communication link to establish a secure channel within the wireless communication link, and the wireless communication device employs logic configured to route the data to the second secure element for processing prior to forwarding the data to the operating system, upon establishing the secure channel.

Enhanced wireless communication security

Methods and apparatus relating to low power optimized voltage regulators are described. In one embodiment, a voltage regulator controller may cause leakage current from a load to drain a capacitor (e.g., coupled in parallel with the load) during a reduced power state.

Low power optimized voltage regulator

The present invention is a memory bus connector for accommodating a memory module that is parallel to a motherboard. The memory bus connector of the present invention has a plurality of individual contacts that act as data signal contacts and/or ground members that connect to the lower portion the parallel memory module. The memory bus connector of the present invention also has a sheet grounding member that connects to the upper portion of the memory module.

High speed bus contact system

A Rambus in-line memory module may be adapted for the smaller board size used for example with portable computers. By using wrong-way routing, the routing can be achieved in a small size while matching impedance between the routings. By grouping signals on one side of the module's printed circuit board and ground and power supplies contacts on another side of the board, performance may be improved.

Small outline memory module

A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.

Changing clock frequency

Small outline rambus in-line memory module

A mechanism for automatically enabling and disabling clock signals includes a driver for providing a clock signal as an output, a gate coupled to the driver, and a sensing circuit coupled to both the output of the driver and to the gate. The sensing circuit provides a signal to the gate responsive to the output being in a first state. The gate then prevents the driver from driving the clock signal responsive to the signal from the sensing circuit. In one embodiment, a generator is coupled to the driver for providing a waveform to the driver. The driver then provides the clock signal based on this input waveform. Additionally, the gate is situated between the generator and the driver. The gate, based on the output of the sensing circuit, can then prevent the waveform from being provided to the driver.

Growing community of inventors

Tigard, OR, United States of America

Raviprakash Nagaraj