Freescale Semiconductor,inc.

R&d 3 LLC

Other

Nxp Usa, Inc.

Qualcomm Incorporated

Ravindraraj Ramaraju

Prashant U Kenkare

David R Bearden

George P Hoekstra

Andrew Christopher Russell

Perry H Pelley

William C Moyer

Troy L Cooper

Shayan Zhang

Jogendra C Sarker

Ambica Ashok

Kenneth R Burch

Charles Eric Seaberg

Frank Kelsey Baker, Jr

Maciej Bajkowski

Hector Adrian Sanchez

Michael D Snyder

Hema Ramamurthy

Kathryn C Stacer

Eric V Fiene

Jeremiah T C Palmer

Sunitha Manickavasakam

Cody B Croxton

David Theodore Blaauw

Vladimir P Zolotov

Alexander Hoefler

Klas Magnus Bruce

Bradley J Garni

Edmund Joseph Gieske

Rakesh Vattikonda

Jianan Yang

Thomas W Liston

Harshat Pant

Qadeer A Qureshi

Rajat Chaudhry

Rajendran Panda

Huy Nguyen

De Lu

Ajay Joshi

Michael Garrett Neaves

Mark W Jetton

Peter M Ippolito

Samrat Sinharoy

Reinaldo Silveira

Kent Li

Masoud Zamani

David P Burgess

Henning F Spruth

Mihir A Pandya

David F Greenberg

Bo Pang

Gary A Mussemann

Ravi Gupta

Venkataram Mooraka

Arthur R Piejko

Mihir S Sabnis

Luis Filipe Brochado Reis

Tuck Boon Chan

Mayank Sen Sharma

Bobak A Nazer

Elhossin Abdelmonem Elshafey

Vu N Tran

George P Hockstra

Elham Zamanidoost

Jeremiah T Palmer

Bradford D Hunter

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

The present disclosure relates to methods of mining a block of a distributed ledger. The methods include: receiving a block to be mined, the block including a header hash and a plurality of transactions; creating a first signature based on a first function, where inputs to the first function include the header hash and the plurality of transactions; and creating a second signature based on a second function, where an input to the second function is the first signature. In one example, the second function is a multiplicative inverse function and the method further includes creating the second signature that is a multiplicative inverse value of the first signature with respect to a first irreducible polynomial. The method additionally includes creating a chain of signatures, where each of the signatures is a multiplicative inverse value of a previous output with respect to a respective irreducible polynomial.

Digital data management

A glitch absorbing buffer reduces glitch power in digital circuits. The glitch absorbing buffer includes a logic element configured to identify a digital logic glitch and a delay circuit configured to selectively delay one input to a logic element. The amount of delay imposed is equivalent to a pulse width of the glitch. A Schmitt trigger may amplify the low pass behavior on the input.

Reducing glitch power in digital circuits

Certain aspects are directed to a time-to-digital converter (TDC) that allows for a more accurate jitter measurement. The TDC generally includes a ring oscillator (RO) having a plurality of taps and configured to generate a plurality of RO signals at the plurality of taps, a counter having an input coupled to an oscillating node, and at least two sampling circuits, each having an input coupled to an output of the counter. In certain aspects, the at least two sampling circuits are configured to sample a count signal at the output of the counter based on at least two of the plurality of RO signals at the plurality of taps.

Multi-phase sampling time-to-digital converter (TDC) for jitter measurement

Methods, devices, and systems are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine a corresponding signal value on another node causing the voltage change. In an example the circuit device includes a first circuit configured to couple, when enabled, a signal value onto a first node, and a read circuit having an input coupled to the first node. The read circuit is configured to effect a voltage transition of a signal node at a variable rate corresponding to the voltage of the first node, and to determine the signal value based upon a time-to-transition measurement of the signal node.

Method and circuit device incorporating time-to-transition signal node sensing

Growing community of inventors

Round Rock, TX, United States of America

Ravindraraj Ramaraju