Rambus Inc.

Apple Inc.

Ravindranath T Kollipara

David A Secker

Suresh Rajan

Ian P Shaeffer

Amir Amirkhany

Steven Cameron Woo

Abhijit Mukun Abhyankar

Belgacem Haba

David Nguyen

Ming Chu Li

Kyung Suk Oh

Thomas J Giovannini

John M Wilson

Lei Luo

Farshid Aryanfar

Sanjay Dabral

Chi-Ming Yeung

Mahesh S Hardikar

Donald R Mullen

Arun Vaidyanath

Ralf M Schmitt

Yoshie Nakabayashi

Robert R Atkinson

Minghui Han

Shajith Musaliar Sirajudeen

Joong-Ho Kim

Rajasekaran Swaminathan

Adrian F Torres

Xingchao (Chuck) Yuan

Multi-chip modules and methods of fabrication are described. The MCM may include a plurality of dies in which die-to-die routing can be partitioned within multiple metal routing layers for shorter die-to-die routings, while longer die-to-die routing can be routed primarily in a single metal routing layer. The plurality of dies may also be arranged in a spaced apart relationship to accommodate additional wiring area, while preserving direct routing areas for the longer die-to-die routing.

Scalable large system based on organic interconnect

A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Folded memory modules

Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

High performance, high capacity memory modules and systems

The connector portion of a flex connector may be integrated into a socket, by forming a complete cutout in the socket in which the connector is located, or by forming the socket with a portion having a reduced thickness relative to the rest of the socket, with the connector being positioned in this portion of reduced thickness between the socket and an MLB. Another flex connector may be formed vertically above the first flex connector, mounted to the top surface of the package and clamped in place by a heat sink on top of the stack. Providing both top and bottom flex connectors may multiply the number of available connections for a given footprint. A heatsink positioned on top of the stack may include a spring assembly on a bottom portion to engage specified portions of the stack with a predefined force to ensure correct loading.

Socket with integrated flex connector

Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

Memory mirroring

System and method for dynamic termination control to enable use of an increased number of memory modules on a single channel. In some embodiments, six or eight DIMMs are coupled to a single channel. The dynamic termination scheme can include configurations for input bus termination (IBT) on each of the memory modules for the address bus/command bus and configurations for on-die termination (ODT) one each of the memory modules for the data bus.

Dynamic termination scheme for memory communication

Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

Memory mirroring utilizing single write operations

Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.

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Fremont, CA, United States of America

Ravindranath T Kollipara