Avago Technologies General IP (singapore) Pte. Ltd.

Lsi Logic Corporation

Emulex Design & Manufacturing Corporation

Ravindra Sadanand Shenoy

Chaitanya Tumuluri

Parag Bhide

Mukund T Chavan

Ashwin Kamath

Sujith Arramreddy

Anthony Hurson

Chih-Jen Hung

Ganesh Boddapati

A rate limiter incorporated in a server connected to a network. The rate limiter is adapted to reduce congestion in the network in response to a congestion notification message. The server is adapted to send packets over the network. The rate limiter includes at least one of: a server rate limiter engine adapted to rate limit the packets in response to the server; a virtual machine rate limiter engine adapted to rate limit the packets in response to a virtual machine associated with the packets, the virtual machine hosted by the server; a flow rate limiter engine adapted to rate limit the packets in response to a flow associated with the packets; the flow being one of a plurality of flows transporting packets over the network; and a transmit engine adapted to rate limit the packets in response to a virtual pipe of the network for transmitting the packets.

Method and system for controlling traffic over a computer network

When interfacing with a host, a networking device can handle a first data like Bulk Data Receive. The networking device can receive the first data and read a first queue entry from a receive queue in the host memory. In response to the read first queue entry, the networking device can write the first data to an unpinned memory in the host memory. The networking device can also handle a second data with a Receive Packet in Ring (RPIR) queue. The networking device can receive the second data and write the second data to a pinned memory in the host memory. The RPIR queue can be separate from or overlaid on the receive queue. High throughput and low-latency operation can be achieved. The use of a RPIR queue can facilitate the efficiency of resource utilization in the reception of data messages.

Low-latency packet receive method for networking devices

A hardware switch for use with hypervisors and blade servers is disclosed. The hardware switch enables switching to occur between different guest OSs running in the same server, or between different servers in a multi-root IOV system, or between different guest OSs running in the same server in single-root IOV systems. Whether embedded in a host bus adapter (HBA), converged network adapter (CNA), network interface card (NIC) or other similar device, the hardware switch can provide fast switching with access to and sharing of at least one external network port such as a Fibre Channel (FC) port, 10 Gigabit Ethernet (10 GbE) port, FC over Ethernet (FCoE) port, or other similar port. The hardware switch can be utilized when no hypervisor is present or when one or more servers have hypervisors, because it allows for switching (e.g. Ethernet switching) between the OSs on a single hypervisor.

Hardware switch for hypervisors and blade servers

An oscillator circuit includes an electrical load, a first metal oxide semiconductor (MOS) devise, a second MOS device, and a negative feedback circuit. The electrical load is coupled between a first node and a second node. The first MOS device is coupled between the first node and a third node, and controls a first current flowing from the first node to the third node. The second MOS device is coupled between the second node and a fourth node, and controls a second current flowing from the second node to the fourth node. A positive feedback circuit is formed with the first and second MOS devices. The positive feedback circuit has inputs from the first and second nodes and outputs to the first and second MOS devices. The negative feedback circuit has inputs from the third and fourth nodes and outs to the first and second MOS devices.

Oscillator circuit with flicker noise suppression and method for operating the same

Growing community of inventors

Costa Mesa, CA, United States of America

Ravindra Sadanand Shenoy