International Business Machines Corporation

Ravindra K Nair

Se June Hong

Eugene Shapiro

Martin Edward Hopkins

Kin Shing Chan

Gregory F Grohoski

A method and apparatus for prefetching superblocks in a computer processing system having a fetch mechanism for fetching instructions for execution includes the step of controlling the fetch mechanism to begin fetching at a starting address of a current superblock. A superblock includes a set of instructions in consecutive address locations terminated by a branch instruction known to have been taken. A Superblock Target Buffer (STB) is supplied with the starting address of the current superblock. The STB has a plurality of entries each indexed by a starting address of a superblock and including a run length of the superblock and a target address of the terminating branch of the superblock. The run length corresponds to the sum of a length of the terminating branch and the difference between a starting address of the terminating branch of the superblock and the starting address of the superblock. It is then determined whether or not the starting address of the current superblock supplied to the STB matches a starting address indexing an STB entry. A starting address of a next sequential superblock is determined by summing the starting address of the current superblock and the run length specified in the STB entry, when the starting address of the current superblock supplied to the STB matches the starting address indexing the STB entry. The fetch mechanism is controlled to end fetching at the starting address of the next sequential superblock.

Method and apparatus for prefetching superblocks in a computer processing system

A method for associating subroutine calls with corresponding targets includes the step of maintaining a first table of entries. Each entry in the first table includes: a first table first address identifying an entry point address for a corresponding subroutine; and a first table second address identifying a return address of a return for the corresponding subroutine. A second table of entries is also maintained. Each entry in the second table includes: a second table first address identifying a return address of a return for a respective subroutine called by a corresponding subroutine call instruction; a second table second address identifying a target address of the return for the respective subroutine; and a second table third address identifying an entry point address for the respective subroutine. It is determined whether the second table stores an entry whose second table first address corresponds to a return address of a return for a considered subroutine. If so, a target address of the return for the considered subroutine is predicted to be the second table second address of the corresponding entry.

Method and apparatus for subroutine call-return prediction

Dynamically typed registers in a processor are provided by associating a type specifier with a register specifier for each register in the processor, storing the register specifiers and associated type specifiers in a register type table. The type specifier associated with an operand register of an instruction is employed to dispatch the instruction to an appropriate execution unit within the processor. The results of the instruction are stored in a register having an associated type specifier matching the execution unit type. Register specifiers are dynamically allocated to particular execution units within the processor by altering the type specifier associated with the register specifiers. Register values may be either discarded or converted when the register specifier type is altered. A general instruction allows conversion of the value from one type to another without storing the converted value in memory.

Dynamically typed register architecture

In response to reloading an instruction from main memory for storing in an instruction cache in a superscalar data processing system, a particular instruction category in which the instruction belongs is selected from multiple instruction categories. Types of data processing system resources required for instruction execution and a quantity of each type of resource required are determined. Thereafter, a plurality of decode bits are calculated, wherein the decode bits represent a particular instruction category in which the instruction belongs and the type and quantity of each data processing system resource required for execution of the instruction. Thereafter, the instruction and the predecode bits are stored in instruction cache. The predecode bits enable the dispatch unit to efficiently, and without fully decoding the instruction at dispatch time, select an execution unit for executing the instruction and determine if the data processing system resources required for execution of the instruction are available before the dispatch unit dispatches the instruction.

Methods and system for predecoding instructions in a superscalar data

A small buffer called a branch-anticipate buffer (BAB) is used to store groups of instructions which are likely to be required from the instruction cache (I-cache) when an instruction prefetch miss occurs. When a prefetch miss occurs, the BAB is checked to see if instructions corresponding to the target address are available. If they are available, these instructions are copied into an appropriate buffer. If the instructions corresponding to the target address are unavailable, these instructions are fetched from the I-cache and placed into a buffer and, selectively, into the BAB. The BAB only maintains branch target addresses that have not been previously scanned and that cannot be prefetched in time. This allows for smaller buffer sizes, and resulting quicker access time, when checking the BAB for instructions to be executed by a processor.

Method and apparatus for managing the execution of instructons with

A computer processing apparatus includes a buffer called a decoded instruction buffer (DIB), which is used to store groups of commands representing instructions that can be executed in parallel. Each pattern in a DIB group may be an encoding of a long instruction termed a long decoded instruction (LDI). The DIB works in conjunction with a conventional computer processing apparatus consisting of a memory system, an instruction queue, and an instruction dispatch unit feeding into a set of execution units. When an instruction is not available in the DIB, this and subsequent instructions are fetched from the memory system into the instruction queue and executed in a conventional way. Simultaneous with the execution of instructions by the conventional apparatus, a group formatter creates a set of LDIs, each of which is an alternate encoding of a set of the original instructions which can be executed in parallel. In constructing the LDIs, the group formatter analyzes the dependency between instructions and instruction latency. Each set of LDIs constructed by the group formatter is saved in the DIB so that the next execution of the same set of instructions can be executed directly from the DIB on the full complement of functional units and will not require the effort of dependency and latency analysis.

Computer processing system employing dynamic instruction formatting

A method of generating the layout of CMOS cells from a high-level functional description of the cells, as well as generating the particular details of the CMOS device. In particular, the image of the chip is formed having the polysilicon gates of the transistors on the n-side vertically aligned with those of the p-side vertically aligned with those of the p-side to minimize the wiring effort. The interconnections between the source and drains are orthogonal to the gates, and run along one layer of metal.

Automated book layout in static CMOS

Method and apparatus for the physical design of very large scale integrated (VLSI) circuits, and in particular the interconnection and wire routing between circuits formed on a chip. Apparatus is set forth for determining the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with n, where n is an integer, identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbor processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned. The array of processors may be utilized to wire a much larger array of cells.

High speed machine for the physical design of very large scale

A method and apparatus for very rapidly determining a minimum or maximum data word from a list of such words in which the expected time for completing the determination of the minimum or maximum value decreases as the number of words in the list is increased. Each data word is stored in a dedicated processing element. Each processing element first outputs onto an open-collector bus a '0' in a position corresponding to the highest order '1' bit in the stored data word. The data signal thus assembled on the bus thus has a '0' at positions corresponding to the highest order '1' bit of each of the processing elements. In response to this data signal, a single controller transmits back to the processing elements a control signal having a '0' in and only in the lowest order '0' bit of the data signal received on the bus. In the processing elements, ones of the processing elements which have a '1' bit in a higher position than the single '0' bit of the control signal are eliminated, while in processing elements still active, ' 1' bits are eliminated from the stored data word in the same position as the '0' of the control signal. The most significant '1' bit of the modified control word in each processing element is again determined, and the process repeated until only a single processing element, or multiple processing elements in which the same data word is stored, is left transmitting back to the controller. In that processing element is stored the minimum or maximum data word.

Method and apparatus for determining minimum/maximum of multiple data

Method and apparatus for the physical design of very large scale integrated (VLSI) circuits, and in particular the interconnection and wire routing between circuits formed on a chip. Apparatus is set forth for determining the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with n, where n is an integer, identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbor processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned. The array or processors may be utilized to wire a much larger array of cells.

Growing community of inventors

Briarcliff Manor, NY, United States of America

Ravindra K Nair