Xilinx, Inc.

Ravinder Sharma

Sebastian Turullols

Ramesh R Subramanian

Jayaram Pvss

Ch Vamshi Krishna

Kaustuv Manji

Siva Santosh Kumar Pyla

Ashish Banga

Manjunath Chepuri

Sonal Santan

Stephen P Rozum

Kyle Corbett

Ravi Nagarajarao Kurlagunda

Brian S Martin

Sudipto Chakraborty

Rishabh Gupta

Cheng Zhen

Deboleena Minz Sakalley

Min Ma

Susheel Kumar Puthana

Ashif Khan Mohammed

Michael Zapke

Indlamuri Hemanth Kumar

Himanshu Choudhary

Amit Kumar

Alagar Rengarajan

Gokul Kavungal Nechikott

Saifuddin Kaijar

Suraj Patel

Kaustuvmani Manji

Raj Kumar Rampelli

Pranjal Joshi

Nilay Shah

Naga Murali Narasimha Rao Medeme

Methods and systems to manage an environmental condition, such as power consumption and/or temperature, of an integrated circuit (IC) device by controlling a bandwidth of a packet-based communication interface of the IC device (e.g., a PCIe interface). Bandwidth may be controlled by controlling delay between packets or controlling delay of a handshake signal. Delay may be increased when the environmental condition reaches a first threshold. Delay may be reduced when the environmental condition falls to a second threshold. Bandwidth may be regulated with proportional-integral control provided by a firmware controller and/or hardware. Bandwidth may be separately controlled for upstream and downstream paths based on bandwidth utilization of the respective paths. Bandwidth control may utilize codes stored in selectable registers. The IC device may include a field programmable gate array (FPGA) and may be configured as an accelerator card.

Power and temperature driven bandwidth throttling using delay insertion

Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

Flat shell for an accelerator card

Embodiments herein describe techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as 'cards') by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds.

Power and temperature driven clock throttling

Changing accelerator card images without rebooting a host system includes receiving, within an integrated circuit (IC) of an accelerator card, an address of a platform image stored in a non-volatile memory of the accelerator card. The address is received over a communication link between the host system and the accelerator card while the communication link is connected. Changing accelerator card images includes detecting, within a register of the IC, that a warm boot enable flag is set and that the communication link with the host system is disconnected. In response to detecting that the warm boot enable flag is set and that the communication link is disconnected, loading of the platform image from the address of the non-volatile memory into the integrated circuit is initiated.

Changing accelerator card images without host system reboot

A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

High throughput circuit architecture for hardware acceleration

A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.

Method and apparatus for direct memory access transfers

A network device includes a first port, a second port, a third port, and an arbitration circuit. The arbitration circuit is configured to receive a first frame and a second frame. The first frame is received from the first port and to be forwarded to the third port. The second frame is received from the second port and to be forwarded to the third port. The arbitration circuit compares a first priority of the first frame and a second priority of the second frame to generate a first comparison result. In response to the first comparison result, first forwarding data is generated based on the first and second frames. The first forwarding data is sent to an output of the arbitration circuit.

Systems and methods for frame buffering and arbitration in a network

A time-sensitive networking system includes gate control circuits configured to control egress of data from multiple queues, respectively. A list execution circuit configures gate states of the plurality of gate control circuits based on a current gate control list that specifies a sequence of operations. Each operation specifies the gate states of the gate control circuits. A cycle timer circuit transmits a timing signal that signals to start a gating cycle by the list execution circuit. A list configuration circuit inputs a new gate control list and establishes the new gate control list as the current gate control list. The list configuration circuit transmits an initial cycle start signal directly to the list execution circuit, bypassing the cycle timer circuit, in response to completion of establishing the new gate control list as the current gate control list.

Time sensitive networking control circuitry

A network device includes a first port, a second port, and a traffic policer circuit. The traffic policer circuit is configured to provide a frame credit and a credit state associated with the frame credit, receive a start of a first frame of a first stream from the first port, and determine a first estimate frame length of the first frame based on the frame credit and credit state. After the first estimate frame length is generated and prior to an end of the first frame is received, the first frame is metered based on the first estimate frame length to mark the first frame with a first marking. After the end of the first frame is received, the frame credit and credit state are updated based on the first frame. The first frame is forwarded to the second port by policing the first frame based on the first marking.

Systems and methods for policing streams in a network

A method, computing device, and non-transitory computer-readable medium for arbitrating data for channels in a video pipeline. The method includes determining arbitration weights for the channels. The method also includes determining which channels have arbitration weights above a threshold. The method further includes issuing data to the channels with arbitration weights above the threshold. The method also includes decrementing arbitration weights for channels for which data is issued. The method further includes repeating the determining, issuing, and decrementing until no channels have arbitration weights above the threshold.

Adaptive video direct memory access module

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Hyderabad Telangana, India

Ravinder Sharma