Advanced Micro Devices Corporation

Globalfoundries Inc.

Ravinder Reddy Rachala

Stephen Victor Kosonocky

Shawn Searles

Scott C Johnson

Miguel Rodriguez

Donald H Walters

Jerry D Moench

Stephen C Ennis

Dimitry Patent

Matthew Cooke

Lena Ahlen

Don Walters

Krishnan-Talkad Sukumar

Ankit Kamleshbhai Zalawadiya

A system and method for efficiently measuring on-die power supply voltage are described. In various implementations, an integrated circuit includes power supply monitors across a die of the integrated circuit. A power supply monitor receives a power supply voltage and generates a code indicating a value of the power supply voltage. A first ring oscillator receives the power supply voltage and a pulse used as an enable signal. A pulse generator of the power supply monitor takes into account the process, voltage and temperature (PVT) characteristics of the integrated circuit by including at least a second ring oscillator and a modulus counter that receives an output of the second ring oscillator. Therefore, the pulse generated by the pulse generator is PVT dependent and increases gain of the power supply monitor.

On-die power supply monitor design

A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.

Time domain multiply and accumulate system

A system and method for measuring power supply variations are described. A functional unit includes one or more power supply monitors capable of measuring power supply variations. The power supply monitors forego use of a clock signal from clock generating circuitry and forego use of a reference voltage from a reference power supply. The power supply monitors use an output of a source ring oscillator as a clock signal for the sequential elements of a counter. The counter measures a number of revolutions of a measuring ring oscillator within a period of the output of the source oscillator. The revolutions of the measuring ring oscillator are associated with a number of rising edges and falling edges of the output signal of the measuring ring oscillator. An encoder converts the output of the sequential elements to a binary value, and sends the binary value to an external age tracking unit.

Reference free and temperature independent voltage-to-digital converter

In one form, a power supply monitor including a current controlled oscillator circuit, a time-to-digital converter, and an output divider. The current controlled oscillator circuit has an input for receiving a power supply voltage to be measured, and an output for providing a frequency signal having a frequency linearly proportional to the power supply voltage. The time-to-digital converter has an input coupled to the output of the current controlled oscillator circuit, and an output for providing a count signal representative of a number of cycles of a reference clock signal per cycle of the frequency signal. The output divider has an input coupled to the output of the time-to-digital converter, and an output for providing a divided count signal representative of a value of the power supply voltage, and provides the divided count signal by dividing a fixed number by the count signal.

Linear, low-latency power supply monitor

A temperature sensor has a first transistor with a gate voltage tied to maintain the first transistor in an off state with leakage current flowing through the transistor, the leakage current varying with temperature. A second transistor is coupled to the first transistor and receives a gate voltage to keep the second transistor in an on state. A current mirror mirrors the leakage current and supplies a mirrored current used to control a frequency of an oscillator signal varies with the mirrored current. The temperature of the first transistor is determined based the frequency of the oscillator signal.

Compact supply independent temperature sensor

A calibrated temperature sensor includes a power on oscillator responsive to a calibration enable signal for providing a power on clock signal, a temperature dependent oscillator responsive to said calibration enable signal for providing a temperature dependent clock signal, and a measurement logic circuit. The measurement logic circuit counts a first number of pulses of the temperature dependent clock signal during a first calibration period using the power on clock signal, a second number of pulses of the temperature dependent clock signal during a second calibration period using a system clock signal, and a third number of pulses of the power on clock signal over a third calibration period using the system clock signal, and a fourth number of pulses of the temperature dependent clock signal using the system clock signal during a normal operation mode, wherein the first calibration period precedes both the second and third calibration periods.

Accurate on-chip temperature sensing using thermal oscillator

A processor system includes first and second regulators for regulating an adjusted supply voltage. In one embodiment, the regulator system comprises a digital low-dropout (DLDO) control system comprising first and second regulators that generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value. The first regulator implements a first control loop and the second regulator implements a second and much faster acting control loop. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply.

Droop detection for low-dropout regulator

Clock skew may be detected measured and compensated for using phase detectors and variable delay adjusters. Phase detectors may be distributed throughout a clock distribution network and may be configured to analyze two clock signals to determine how often one signal leads the other. The output of the phase detectors may be measured and counted over a large number of clock cycles. The difference between the number of times one signal leads or lags behind the other may be used to determine the amount of delay to apply to the leading clock signal in order to minimize (reduce) skew between the two clock signals. The same techniques for detecting and measuring clock skew may also be used to detect and measure jitter in the clock signals. By configuring variable delay adjusters on clock signals, the amount of jitter in the clock signals can be measured or characterized.

Controller for clock skew determination and reduction based on a lead count over multiple clock cycles

A system and method for using variable delay adjusters located at various points across an integrated circuit to measure clock skew and jitter for clock signals of the integrated circuit. A delay controller of the integrated circuit may measure and compensate for clock skew detected between two clock signals by configuring variable delay adjusters located inline with the respective clock signals. Such a delay controller may also use the variable delay adjusters to correct duty cycle errors in a clock signal and may further utilize the variable delay adjusters to measure and characterize jitter detected on the clock signals.

Incrementally adjustable skew and duty cycle correction for clock signals within a clock distribution network

An electronic circuit. The electronic circuit includes a first circuit leg coupled to a first supply voltage node and a second supply voltage node. The first circuit leg includes a first reference current circuit configured to produce a first reference current and a second reference current circuit configured to produce a second reference current. The electronic circuit further includes a second circuit leg coupled in parallel with the first circuit leg. The second circuit leg includes a first transistor coupled to form a current mirror with the first reference current circuit and a second transistor coupled to form a current mirror with the second reference current circuit. The source terminals of each of the first and second transistors are coupled together to form a third supply voltage node.

Voltage source for gate oxide protection

Various embodiments of methods and systems for providing virtual leaf driver nodes in a clock tree to drive a clock grid of an integrated circuit are disclosed. An integrated circuit may include a large number of clocked elements such as registers, flip-flops, etc. whose operation is synchronized by one or more clocks. For example, an operation performed by circuitry on one side of the die may need to occur at precisely the same time as another operation performed by circuitry on the other side of the die. In order to assure synchronicity of these events, a clock grid may be provided in the IC that is driven by virtual leaf driver nodes. The clock tree driving the clock grid may include a tier of leaf buffers. The output of a leaf buffer may be split, and the branches of the output connected to separate points on the clock grid.

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Austin, TX, United States of America

Ravinder Reddy Rachala