International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies Ag

Siemens Aktiengesellschaft

Other

Infineon Technologies North America Corp.

Freescale Semiconductor,inc.

Ravikumar Ramachandran

Reinaldo Ariel Vega

Emre Alptekin

Ramachandra Divakaruni

Unoh Kwon

Henry K Utomo

Kangguo Cheng

Richard Stephan Wise

Viraj Yashawant Sardesai

Vijay Narayanan

Rajasekhar Venigalla

Albert Manhee Chu

Hiroyuki Akatsu

Myung-Hee Na

Ruilong Xie

Dechao Guo

Michael Patrick Chudzik

Andrew Mark Greene

Siddarth A Krishnan

David Lee Rath

Ying Li

Kenneth T Settlemyer, Jr

Ali Khakifirooz

Julien Frougier

Kern Rim

Renee Tong Mo

Shahab Siddiqui

Gregory Costrini

Junli Wang

Carl John Radens

Theodorus E Standaert

Oleg Gluschenkov

Herbert Lei Ho

Laertis Economikos

John Anthony Fitzsimmons

Wesley Charles Natzle

Xinhui Wang

Hongwen Yan

Oh-Jung Kwon

Yue Liang

Brent A Anderson

Takashi Ando

Huilong Zhu

Veeraraghavan S Basker

Kevin K Chan

Shom Ponoth

Balasubramanian Pranatharthiharan

Keith Kwong Hon Wong

Sanjay C Mehta

Su Chen Fan

Zhengwen O Li

John Edward Barth, Jr

Thomas W Dyer

Helmut Horst Tews

Balasubramanian S Haran

Min Yang

Dae-Gyu Park

Johnathan E Faltermeier

Byeong Yeol Kim

Chun-Yung Sung

Naim Moumen

Eric Peter Solecky

Stefan Schmitz

Michael Vincent Aquilino

Alexander William Simpson

Effendi Leobandung

Daniel C Edelstein

Rajiv V Joshi

Jeffrey W Sleight

Nicolas J Loubet

Yun Yu Wang

Haining S Yang

Lars W Liebmann

Sivananda K Kanakasabapathy

Ruqiang Bao

Soon-Cheon Seo

Injo Ok

Jeffrey Bowman Johnson

Martin Michael Frank

Shreesh Narasimha

Babar Ali Khan

Kisik Choi

Eduard Albert Cartier

Kafai Lai

Chandrasekhar Narayan

Richard Anthony Conti

Barry P Linder

Michael P Belyansky

William K Henson

David M Dobuzinsky

William J Cote

Albert M Young

Charan V V S Surisetty

Nicolas Nagel

Keith Howard Tabakman

Xian Jay Ning

Christopher Carr Parks

Cung D Tran

Xi Li

Jeremy K Stephens

A microelectronic structure including a plurality of lower transistors and a plurality of upper transistor, where each of the plurality of lower transistors and the plurality of upper transistors includes a plurality of channel. Where an upper center vertical axis of each of the plurality of upper transistors is staggered from a lower center vertical axis of each of the lower transistors. A lower gate cut is located between each of the plurality of lower transistors. A first upper gate cut located adjacent to a first upper transistor of the plurality of upper transistors, where the first upper gate cut is in direct contact with a plurality of first channels of the first upper transistor.

Method and structure of forming independent contact for staggered CFET

A microelectronic structure including a stacked transistor having a lower transistor and an upper transistor. A shared contact in contact with a lower source/drain of the first lower transistor and an upper source/drain of the upper transistor. The shared contact includes a silicide layer, a metal plug layer, and a conductive metal layer.

Method and structure of forming sidewall contact for stacked FET

A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first side of the front-end-of-line level. A backside power rail is embedded within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. At least one backside field effect transistor is formed on a first semiconductor layer disposed, at least in part, above a passive device region. A first side of the passive device region is in contact with the first semiconductor layer and a second side of the passive device region, opposing the first side, is in contact with the back-end-of-line interconnect level.

Semiconductor backside transistor integration with backside power delivery network

A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

Stacked FET SRAM

A first semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a second high-κ dielectric layer over the first high-κ dielectric layer, a Ti—Si mixing layer over the second high-κ dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-κ dielectric layer, a second high-κ dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-κ dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-κ dielectric layer over the interfacial layer, forming a second high-κ dielectric layer over the first high-κ dielectric layer, and forming a gate electrode layer over the second high-κ dielectric layer.

Gate stacks with multiple high-κ dielectric layers

A stacked device is provided. The stacked device includes a reduced height active device layer, and a plurality of lower source/drain regions in the reduced height active device layer. The stacked device further includes a lower interlayer dielectric (ILD) layer on the plurality of lower source/drain regions, and a conductive trench spacer in the lower interlayer dielectric (ILD) layer, wherein the conductive trench spacer is adjacent to one of the plurality of lower source/drain regions. The stacked device further includes a top active device layer adjacent to the lower interlayer dielectric (ILD) layer, and an upper source/drain section in the top active device layer. The stacked device further includes a shared contact in electrical connection with the upper source/drain section, the conductive trench spacer, and the one of the plurality of lower source/drain regions.

High aspect ratio shared contacts

Embodiments of present invention provide a SRAM device. The SRAM device includes a first, a second, and a third SRAM cell each having a first and a second pass-gate (PG) transistor, wherein the second PG transistor of the second SRAM cell and the first PG transistor of the first SRAM cell are stacked in a first PG transistor cell, and the first PG transistor of the third SRAM cell and the second PG transistor of the first SRAM cell are stacked in a second PG transistor cell. The first and second PG transistors of the first SRAM cell may be stacked on top of, or underneath, the second PG transistor of the second SRAM cell and/or the first PG transistor of the third SRAM cell.

Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.

FinFET based ZRAM with convex channel region

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate cut mask having one cut window exposing one or more portions of multiple sacrificial gate structures of the at least one plurality of sacrificial gate structures. The multiple sacrificial gate structures having been formed over portions of in structures. The method comprises forming a gate cut mask a plurality of semiconductor fins and a plurality of sacrificial gate structures. The gate cut mask being formed with one cut window exposing one or more portions of multiple sacrificial gate structures of the plurality of sacrificial gate structures. At least the portion of multiple sacrificial gate structures and one or more portions of each semiconductor fin of the plurality of semiconductor fins underlying the one or more portions of one of the multiple sacrificial gate structures are removed.

Fabricating tapered semiconductor devices

A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.

Reliable gate contacts over active areas

A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET structure includes one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finFET structure. The method also includes performing a fin cut by removing a portion of at least one fin. The portion of the at least one fin is determined by an exposed area of the fin cut mask. The exposed area of the fin cut mask includes at least a portion of the at least one fin between a first dummy gate and a second dummy gate formed over the at least one fin. The method further includes removing the fin cut mask and depositing an oxide to replace the portion of the at least one fin removed during the fin cut.

Preserving channel strain in fin cuts

A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.

Standard cell architecture with at least one gate contact over an active area

Finfet based ZRAM with convex channel region

Growing community of inventors

Pleasantville, NY, United States of America

Ravikumar Ramachandran