Advanced Micro Devices Corporation

Redback Networks Inc.

Ravikrishna Cherukuri

Ranjit Joseph Rozario

Stuart F Oberman

Ming Siu

Frederick Daniel Weber

Norbert Juffa

Edmund G Chen

Sridhar P Subramanian

Ruchi Wadhawan

Scott Waldron

Gregory G Minshall

A scheduler configured to schedule multiple channels of a Direct Memory Access (DMA) device includes a shift structure having entries corresponding to the multiple channels to be scheduled. Each entry in the shift structure includes multiple fields. Each entry also includes a weight that is determined based on these multiple fields. The scheduler also includes a comparison-logic circuit that is configured to then sort the entries based on their respective weights.

Scheduler for a direct memory access device having multiple channels

A method and apparatus for replicating packet data within a network element are described herein. In one embodiment, a method includes storing packet data within a storage element, maintaining a transmit count value of the storage element, determining a release count value of the storage element, comparing the transmit count value and the release count value, and de-allocating the storage element in response to comparing the transmit count value and the release count value.

Method and apparatus for replicating packet data with a network element

A method and apparatus for sharing memory space of multiple memory units by multiple processing units are described. In an embodiment, a method includes storing a set of data across more than one of at least two memory units upon determining that the number of sets of data is static. The method also includes storing the set of data within a single memory unit of the at least two memory units upon determining that the set of data is dynamic.

Method and apparatus for sharing memory space across mutliple processing units

A method and apparatus for transmitting unscheduled flow control, in packet form, between two chips are described. In one embodiment, a method includes reading a status of a buffer used to receive network packets transmitted from a different chip. The method further includes transmitting to said different chip an unscheduled flow control packet including information about the status of the buffer. In an embodiment, a chip includes a packet buffer to store network packets transmitted from a different chip, wherein the packet buffer is associated with one or more of a plurality of ports through which the network packets travel. The chip also includes control circuitry, coupled with a packet data bus to receive said network packets from the different chip, and coupled with an unscheduled flow control packet bus to generate and transmit unscheduled flow control packets to the different chip, wherein the unscheduled flow control packets contain information relating to the packet buffer.

Method and apparatus for unscheduled flow control in packet form

A method and apparatus for controlling the admission of data packets into a network element is described. In an embodiment, a method for controlling admittance of a data packet into a memory buffer includes performing, prior to queuing the data packet for routing by a processor, the following: (1) receiving a data packet from one of at least two different ports, (2) determining a priority value within the data packet, and (3) determining an admittance group identifier for the data packet based on the priority value and the port the data packet was received. The method also comprises queuing the data packet from the memory buffer to one of a number of queues for routing by the processor upon determining that a number of data packets stored in the memory buffer and having the admittance group identifier is not greater than a threshold value.

Method and apparatus for controlling the admission of data into a network element

Free memory can be managed by creating a free list having entries with address of free memory location. A portion of this free list can then be cached in a cache that includes an upper threshold and a lower threshold. Additionally, a plurality of free lists are created for a plurality of memory banks in a plurality of memory channels. A free list is created for each memory bank in each memory channel. Entries from these free lists are written to a global cache. The entries written to the global cache are distributed between the memory channels and memory banks.

Free memory manager scheme and cache

A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur. The multiplier may also be configured to perform iterative calculations to evaluate constant powers of an operand. Intermediate products that are formed may be rounded and normalized in two paths and then compressed and stored for use in the next iteration. An adjustment constant may also be added to increase the frequency of exactly rounded results.

Method and apparatus for rounding in a multiplier

Method and apparatus for calculating a power of an operand

A gear box module or circuit can act as an interface for transferring data from a first clock domain to a second clock domain. The gear box circuit uses a level sensitive memory element coupled to an input selection circuit to receive data from logic in the first clock domain and provide the data to logic in the second clock domain. An input selection signal causes the selection circuit to select the input source for the level sensitive memory element, thereby allowing the proper signal to be provided as output to logic in the second clock domain. Additionally, the gear box can provide the proper output signal for logic in the second domain using circuitry to alternately mask the gear box output. The gear box receives control signals, including for example the input selection signal, from control circuitry. The logic in each clock domain does not have to be aware of the clock frequency on the other side of the gear box, nor does it need to be aware of the ratio of clock frequencies between clock domains. Consequently, the logic in each domain is simplified, the gear box circuit itself can be independent of the gear ratio (i.e., the ratio of clock frequencies), timing delays can be reduced, and metastability can be avoided.

Gear box for multiple clock domains

A system (,) for automatically ordering a request for access to a system memory (,) is disclosed. The system (,) includes a re-ordering buffer (,) having a data input (,) and a data output (,) and an input request position identifier (,) associated with the re-ordering buffer (,). The input request position identifier (,) indicates a position of the data input (,) in the re-ordering buffer (,) for the new request based on a status of the request. A method (,) of ordering a request for access to a system memory (,) in a buffer (,) is also disclosed and includes initiating a request (,) for access to the system memory (,), wherein the request contains a status indicating a priority of the request. The status of the request is evaluated (,) to determine whether the request is a high priority request or a low priority request and a location for inputting the access request into the buffer (,) is identified (,) in response to the evaluation. One or more previously requested access requests are then shifted (,) within the buffer if necessary to make room for the access request at the identified location and the new access request is inserted into the buffer at the identified location (,).

Arbitrating FIFO implementation which positions input request in a buffer according to its status

Method and apparatus for multi-function arithmetic

A method (,) of implementing a set of ordering rules for executing requests for access to a system memory (,) includes the steps of identifying a request status (,) for a new request for access to the system memory (,) and assigning a tag to the new access request (,) based on the status of the new request. A control circuit (,) inserts the new access request (,) into one of a read buffer (,) or a write buffer (,) at a specified location within one or the read or write buffers (,) based on the status of the new access request. When the new access request is enqueued (,) and sent to an arbitration circuit (,), the requests are executed in an order with another access request (,) from the other of the read or write buffer based on the request status and the tag of the new request.

Method for ordering a request for access to a system memory using a reordering buffer or FIFO

A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and comprises a partial product generator, a selection logic unit, and an adder. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. The multiplier is also configured to receive a first control signal indicative of whether signed or unsigned multiplication is to be performed and a second control signal indicative of whether vector multiplication is to be performed. The multiplier is configured to calculate an effective sign for the multiplier and multiplicand operands based upon each operand's most significant bit and the control signal. The effective signs may then be used by the partial product generation unit and the selection logic to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, the adder is configured to sum them and output the results, which may be signed or unsigned. When a vector multiplication is performed, the multiplier is configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.

Method and apparatus for simultaneously performing arithmetic on two or

A computer system includes a mirrored memory system, in which each bank is coupled to a different channel from the one or more microprocessors included in the computer system. Each microprocessor is coupled to a fetch channel for performing fetch operations from one of the mirrored memory banks within the computer system. Additionally, each microprocessor is coupled to a prefetch channel for performing prefetch operations from a different one of the mirrored memory banks. In multiprocessor configurations, the microprocessors may share the fetch channel and/or the prefetch channel, or may be provided with separate channels for either fetch or prefetch operations. Prefetch operations do not interfere with fetch operations from the same microprocessor. Additionally, prefetch operations are not preempted by fetch operations (except for write operations which update all memory banks, if the memory banks do not include write queues). Still further, fetch operations from one microprocessor in a multiprocessor configuration do not interfere with prefetch operations from another microprocessor.

Growing community of inventors

San Jose, CA, United States of America

Ravikrishna Cherukuri