Motorola Corporation

Ravichandran Subrahmanyan

William H Lytle

Shawn O'Rourke

Albert Alec Talin

Kenneth Andrew Dean

Bernard F Coll

Matthew Stainer

Jong-Kai Lin

Ravinder K Sharma

Barry C Johnson

Thomas A Scharr

Russell Thomas Lee

A method of fabricating a field emission device cathode using electrophoretic deposition of carbon nanotubes in which a separate step of depositing a binder material onto a substrate, is performed prior to carbon nanotube particle deposition. First, a binder layer is deposited on a substrate from a solution containing a binder material. The substrate having the binder material deposited thereon is then transferred into a carbon nanotube suspension bath allowing for coating of the carbon nanotube particles onto the substrate. Thermal processing of the coating transforms the binder layer properties which provides for the adhesion of the carbon nanotube particles to the binder material.

FED cathode structure using electrophoretic deposition and method of fabrication

A vacuum microelectronic device ( ) is formed by applying a first conductor ( ) to a substrate ( ) and utilizing the first conductor ( ) to expose a dielectric material ( ) and a second conductive material ( ) from a back surface of the substrate ( ). A second conductor ( ) and a dielectric ( ) are formed from the second conductive material ( ) and the dielectric material ( ), respectively. This method self-aligns the dielectric ( ) and the second conductor ( ) with the first conductor ( ). Electron emitters ( ) of the vacuum microelectronic device ( ) are formed on the first conductor ( ).

Method of forming a vacuum micro-electronic device

Interconnect bumps are formed on a circuit substrate using printing or dispensing techniques with a wet photoresist layer as a mask. A conductive paste is disposed in openings of a wet photoresist layer. The conductive paste is at least partially cured before the wet photoresist layer is removed. Alternatively, the wet photoresist layer may remain if it is a photo-imagable polyimide.

Method of forming an electrical interconnect

A plurality of inserts (12) formed on a first substrate (11). A plurality of sockets (14) formed on a second substrate (13). Each socket of the plurality of sockets (14) on the second substrate (13) has a corresponding insert from the plurality of inserts (12) which physically aligns for coupling. At least one of the first (11) or second (13) substrates must be a semiconductor substrate. This arrangement allows for electrically connecting a semiconductor device or structure to another device for testing, burn-in, or final assembly.

Interconnect system for a semiconductor chip and a substrate

A method for flip-chip bonding an integrated circuit die to a substrate. A substrate (21) having conductive bonding areas (22) coated with tin (23) is secured to a bottom end effector of a flip-chip bonding apparatus. An integrated circuit die (26) having gold bumps (28) is secured to a die tool of the flip-chip bonding apparatus. A gold-tin eutectic bond is formed between the integrated circuit die (26) and the conductive bonding areas (22) of the substrate (21).

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Scottsdale, AZ, United States of America

Ravichandran Subrahmanyan