International Business Machines Corporation

Ravichander Ledalla

Kerim Kalafala

Vasant B Rao

Jeffrey Paul Soreff

Debjit Sinha

Adam P Matheny

Jose Luis Neves

Gregory M Schaeffer

Tsz-mei Ko

Alice Hwajin Lee

Fred Lei Yang

Chandramouli Visweswariah

Jeffrey G Hemmett

Michael H Wood

Philip George Shephard, Iii

Adil Bhanji

Barry Lee Dorfman

Christine T Casey

An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

Incremental parasitic extraction for coupled timing and power optimization

The timing analysis of an integrated chip component using dynamic load sensitive timing feedback constraints maintaining the timing accuracy for all the boundary paths is achieved by capturing a reduced order representation for parasitic load within a component for each of its primary input and primary output along with sensitivities of the arrival time, the slew and the required arrival time to the load representation at the component parent level of hierarchy as part of generating load sensitive feedback constraints. During the out-of-context timing closure of the component, the base load representation and the sensitivities, and an updated load representation enables the calculation of the updated boundary constraint for an accurate timing analysis. The accuracy improvement increases a chip designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing. The method is applicable for deterministic as well as for statistical timing analyses.

Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints

Timing analysis of a chip component using feedback assertions without disrupting the timing of internal latch to latch paths in the chip component maintaining timing accuracy for all the boundary paths. This is achieved by using slack based feedback assertions for non-clock chip inputs and outputs which are used to dynamically derive the arrival time or the required arrival time assertions. The assertions on the clock inputs are not updated via feedback assertions to facilitate non-disruption of the latch to latch path timing. The timing non-disruption of the resulting latch to latch paths of the chip component increases the designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing. This method is applicable for statistical as well as deterministic timing analysis.

Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions

A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.

Timing point selection for a static timing analysis in the presence of interconnect electrical elements

A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.

System and method for improved hierarchical analysis of electronic circuits

A method for further reducing RC parasitics in an interconnect network following internal node elimination is described. A resistor is initially selected as a candidate for shorting, and it is established whether the accumulated delay error at either end of the resistor is less than a predetermined threshold. This threshold must be a fraction of the time-constant threshold selected by internal node elimination techniques in order to limit the growth of the accumulated delay errors. An important aspect of the invention is the simplicity of the formula used to change the downstream resistor values, namely, the product of the value of the resistor shorted and the ratio of the cumulative downstream capacitances of the two ends of the resistor whose value is being changed. This particular choice of updating the downstream resistor values minimizes the absolute-value of the delay errors at every node due to shorting of the selected resistor. It also preserves the delays at all nodes in the interconnect network apart from the two ends of the resistor selected for shorting.

Method for reducing RC parasitics in interconnect networks of an integrated circuit

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Fishkill, NY, United States of America

Ravichander Ledalla