Nxp B.v.

Nxp Usa, Inc.

Ravichandar Reddy Geetla

Deependra Kumar Jain

Charles Eric Seaberg

Gaurav Agrawal

Octavio A Gonzalez

Chang Joon Park

Ravi Kumar

An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

Circuitry and methods for fractional division of high-frequency clock signals

A PID loop filter control method and apparatus are provided for generating a control signal to control a digitally controlled oscillator which generates a phase locked loop clock signal, where the PID loop filter includes a proportional-integral-derivative (PID) controller connected and configured to produce a PID controller output signal, and a transformed feedback module having a feedback summer circuit and internal gain stage connected in series to produce an M-bit control signal in response to the PID controller output signal, wherein an output from internal gain stage is provided over a feedback path comprising a feedback gain stage having a configurable Kfb gain value (e.g., 0&#x3c;Kfb&#x3c;4) and a filter element to produce the internal feedback signal which is summed with the PID controller output signal to low pass filter high frequency spurs and noise from the PID controller output signal.

Modified PID loop filter to suppress high frequency noise in digital phase locked loop

Performing a temperature measurement operation includes a first phase and a second phase. The first phase includes providing a voltage indicative of a measured temperature to a first input of a comparator, providing a ramp signal to a second input of the comparator, and generating at an output of the comparator, pulses based on a comparison of the first input to the second input of the comparator. The second phase includes providing the voltage indicative of a measured temperature to the second input of the comparator, providing the ramp signal to the first input of the comparator, and generating at an output of the comparator, pulses based on a comparison of the first input to the second input of the comparator. Performing the temperature measurement operation also includes utilizing the pulses generated during the first and second phases to provide a digital indication of the measured temperature.

Temperature sensor in an integrated circuit having offset cancellation

A temperature sensor configured to, after a predetermined number of stop counting assertions, determine the temperature dependent voltage and thus the temperature at the output of a counter. During a calibration phase, when a counter value is not equal to a test counter value in a pulse generator circuit, capacitance of the temperature sensor is adjusted until the counter value is equal to the test counter value.

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Austin, TX, United States of America

Ravichandar Reddy Geetla