Cadence Design Systems, Inc.

Atrenta, Inc.

Ravi Varadarajan

Cyrus Soli Bamji

Jitendra Kumar Gupta

Sanjiv Mathur

Kaushal Kishore Pathak

Kshitiz Krishna

Robert Shawn Thompson

Priyank Mittal

Anup Nagrath

Ritesh Mittal

Ashima Dabare

Lenuta Georgeta Claudia Rusu

System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files. Using the results of this top-down global design-closure method the designers can use the generated floor-plan to guide downstream tools to achieve predictable and correlatable design implementation.

Method of global design closure at top level and driving of downstream implementation flow

This invention provides a method for detecting physical implementation hot-spots in a pre-placement integrated circuit design. The method first identifies physical issues at an object level. Physical issues include timing, routing congestion, clocking, scan, power, and thermal. The method then analyzes these physical issues over a collection of connected logic cell and large cell instances and determines a physical implementation hot-spot severity based on the number and severity of physical issues as well as the number of objects in the related collection.

Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis

An electronic design automation method implemented in a computing system is provided for creating a physical connections netlist for a pre-floorplan partitioned design file of 3D integrated circuits. The inputs are a 3D stack defining the topology of multiple dies, and a given design partitioning. The design partitioning defines the logic implemented in each die. The method identifies through-silicon-vias (TSVs), bump pins (BPs) and net connections.

Method for creating physical connections in 3D integrated circuits

A method for the abstraction of connectivity that provides an intermediate data path representation of integrated circuit (IC) designs is provided. The connectivity abstraction maintains the compactness of a bus level representation as well as the uniqueness of a bit level representation. Connectivity abstraction significantly reduces network complexity, i.e., the number of wires in a design and the execution time of physical synthesis of IC designs.

Bus representation for efficient physical synthesis of integrated circuit designs

A computer system, method and software product enables automatic placement and routing of datapath functions using a design methodology that preserves hiearchical and structural regularity in top down designs for datapaths. The system includes a datapath floorplanner, a datapath placer, and routing space estimator. The datapath floorplanner allows the designer to establish and maintain during floorplannning operations datapath regions that include a number of datapath functions each. The datapath floorplanner creates the datapath regions from a netlist specifying logic cell instances and connectivity information, and from a plurality of tile files. A tile file is a structured description of a datapath function, describing the relative vertical and horizontal placement of all logic cell instances within the datapath function. There is one tile file for each unique datapath function. The datapath function instances then are associated with a particular tile file by the tile file list file. The datapath floorplanner uses the tile files to integrate the placement information with the specific function instances, and further allows the specification of clusters, function interleaving, and net side constraints per region. A datapath placer places the datapath functions in each region using the relative placement information and constraints. The routing space estimator estimates the space needed for routing a placed region. All of this information is interactively provided to the circuit designer so as to allow almost real time modification of datapath placement.

Optimized placement and routing of datapaths

A method and system provide for the symbolic design of a symbolic layout of an integrated circuit using only the topological features of the cells of the layout, absent geometrical information. Virtual leaf cells define circuit elements, and virtual hierarchical cells combine virtual leaf cells and other virtual hierarchical cells into hierarchical arrangements using interface graphs. Virtual interfaces describe the connectivity and orientation relations between virtual cells. The interfaces inherit the definitional requirements of interfaces at lower levels. The symbolic layout is produced from a hierarchy of virtual cells using hierarchical compaction and routing technology.

Virtual interface representation of hierarchical symbolic layouts

Overconstraints in a system, such as an electrical circuit layout, are identified using port abstraction graphs. Intercell pitchmatching constraints are represented by meta-edges between cells. Classes of edges which can be represented by a support edge are created, and the value of the class edges are increased to the value of the support edge. The edge values are updated in the graphs, and the redundant edges eliminated. Overconstraints are identified as positive cycles in the graphs, and a database of the layout is annotated and graphically displayed. The graphical display responds to user inputs to manipulate the display of the relations between constraints. The use of the port abstraction graphs also reduces the number of equations that need to be solved to compact the layout.

Identifying overconstraints using port abstraction graphs

A hierarchical pitchmatching compactor is provided that maintains hierarchical structure, design rule correctness, and circuit integrity of a symbolic layout while globally compacting the layout without excessive computational or data handling requirements, even for layouts of substantial size. The compactor achieves this result by taking advantage of the regularity of the layout, to reduce the number of constraints in the linear programming problem to a minimum level. This minimal problem, called the minimum design, can be drastically smaller than the original minimization problem for layouts of practical interest. This technique is implemented by means of a computer program that operates on the original symbolic layout of an integrated circuit to produce an automatically compacted layout as the data output.

Hier archical pitchmaking compaction method and system for integrated

A computer system and computer-implemented method for compacting the geometrical area of a hierarchical integrated circuit layout. The present invention is particularly adapted for use with layouts including over-the-cell routing (OTCR). The inventive method includes the general steps of normalizing the cells, compacting the cells, then reconstructing the layout that includes the normalized cells. More particularly, the step of normalizing the cells includes initial step of identifying an overlapping object produced from the OTCR that overlaps one of the instances. That overlapping object is then divided into an overlapping segment and a non-overlapping segment. The overlapping segment is then removed from the cell and copied into the leaf cell of the overlapped instance. The overlapping segment is defined as a special object of the cell into which it is copied.

Growing community of inventors

Fremont, CA, United States of America

Ravi Varadarajan