Micron Technology Incorporated

Micron Semiconductor, Inc.

Ravi T Iyer

Gurtej S Sandhu

Sujit Sharan

Luan C Tran

Zhiping Yin

Thomas R Glass

Howard E Rhodes

Werner Juengling

Kirk D Prall

Guy T Blalock

Gordon A Haller

Anand Srinivasan

Yongjun Jeff Hu

Randhir P S Thakur

Pai-Hung Pan

Brent D Gilgen

Steven M McDonald

Jigish D Trivedi

Thomas Arthur Figura

Ardavan Niroomand

Hasan Nejad

Charles L Turner

Louie Liu

Sanh D Tang

John Mark Meldrim

Donald L Westmoreland

Prashant Raghu

Richard D Holscher

Pai Hung Pan

Linda K Somerville

Justin Harnish

Durai Vishak Nirmal Ramaswamy

Randhir P Thakur

Brian A Vaartstra

Gilbert Lai

Vishnu Kumar Agarwal

Irina V Vasilyeva

Louie Liù

Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

Silicided recessed silicon

Disclosed is a deposition process for forming a glass film. An embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and exposing the substrate surface to a SiOprecursor gas, a carrier gas, and optionally a dopant gas in the presence of ozone and exposing the reaction volume of the gases above the substrate surface to a high intensity light source.

Methods of forming glass on a substrate

A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

Transistor gate forming methods and transistor structures

A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.

Method to avoid threshold voltage shift in thicker dielectric films

A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

Transistor gate forming methods and integrated circuits

Method of forming a transistor gate of a recessed access device, method of forming a recessed transistor gate and a non-recessed transistor gate, and method of fabricating an integrated circuit

A CVD ozone (O) deposition process, with the preferred embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and exposing the substrate surface to a SiOprecursor gas, a carrier gas, and optionally a dopant gas in the presence of ozone and exposing the reaction volume of the 5 gases above the substrate surface to a high intensity light source, to increase the functional atomic oxygen concentration and reduce the fixed charge in the deposited films.

Methods using ozone for CVD deposited films

Transistor structures

In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si&#x2014;F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si&#x2014;F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si&#x2014;F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si&#x2014;F bonds onto the substrate from the reactants.

Methods of forming fluorine doped insulating materials

The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.

Circuitry and gate stacks

Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

Word lines for memory cells

A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer. Similar methods can further be used in the formation of interconnects to connect contact regions. Gate electrode structures and interconnect structures resulting from the methods are also described. Further, in such methods and structures, the titanium boride layer may be a titanium diboride layer or a titanium boride layer having silicon incorporated therein.

Titanium silicide boride gate electrode

Growing community of inventors

Boise, ID, United States of America

Ravi T Iyer