Adesto Technologies Corporation

Ravi Sunkavalli

Malcolm J Wing

Ed McKernan

Ishai Naveh

A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.

System architectures with data transfer paths between different memory types

Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC.

Network interface with logging

A memory device can include at least two ports for transferring data to and from the memory device; and plurality of memory cells, each memory cell including at least one element programmable between different impedance states, and a plurality of access devices, each access device providing a current path between the element and a different one of the ports.

Multi-port memory devices and methods having programmable impedance elements

A system can include a first memory section comprising a plurality of volatile memory cells accessible via a first data path having a first bit width; a second memory section comprising a plurality of programmable impedance memory cells, each having at least one solid electrolyte layer; and a second data path configured to transfer data between the first and second memory sections independent of the first data path, the second data path having a greater bit width than the first data path.

System architecture with multiple memory types, including programmable impedance memory elements

Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using N bits of the encoded data to store M bits of the data, where M and N are both positive integers and N is greater than M; and (iv) writing the encoded data and the tag in the semiconductor memory device.

Coding techniques for reducing write cycles for memory

A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements.

Memory devices, circuits and, methods that apply different electrical conditions in access operations

A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.

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Cupertino, CA, United States of America

Ravi Sunkavalli