Qualcomm Incorporated

Ravi Sridhara

Bhushan Shanti Asuri

Muhammad Hassan

Gurkanwal Singh Sahota

Abdellatif Bellaouar

Chirag Dipak Patel

Chiewcharn Narathong

Jeremy Darren Dunworth

Lai Kan Leung

Chinmaya Mishra

Jorge Garcia

Jingcheng Zhuang

Arul Balasubramaniyan

Sankaran Aniruddhan

Omar Essam El-Aassar

Li-chung Chang

Jeremy Mark Goldblatt

Frederic Bossu

Ojas Choksi

Babak Nejati

Francesco Gatta

Zhang Jin

Timothy Donald Gathman

Xinmin Yu

Marco Zanuso

Maulin Pareshbhai Bhagat

Tsai-Pi Hung

Xinhua Chen

Mohammad Elbadry

Animesh Paul

Hanil Lee

Sriramgopal Sridhara

Youngchang Yoon

Li-Chung Chang

Ojas M Choksi

Maulin P Bhagat

In certain aspects, a method is provided for measuring power using a resistive element coupled between a power amplifier and an antenna. The method includes squaring a voltage from a first terminal of the resistive element to obtain a first signal, squaring a voltage from a second terminal of the resistive element to obtain a second signal, and generating a measurement signal based on a difference between the first signal and the second signal. In some implementations, the resistive element is implemented with a power switch.

Power detector

In certain aspects, a chip includes a pad, and a power amplifier having a first output and a second output. The chip also includes a transformer, wherein the transformer includes a first inductor coupled between a first terminal and a second terminal of the transformer, wherein the first terminal is coupled to the first output of the power amplifier, and the second terminal is coupled to the second output of the power amplifier. The transformer also includes a second inductor coupled between a third terminal and a fourth terminal of the transformer, wherein the third terminal is coupled to the pad. The chip also includes a first switch coupled to the fourth terminal, a shunt inductor coupled in parallel with the first switch, and a low-noise amplifier coupled to the third terminal.

Switch with electrostatic discharge (ESD) protection

Power detector including squaring circuits

According to certain aspects, a chip includes a pad, a power amplifier, a transformer coupled between an output of the power amplifier and the pad, a transistor coupled between the transformer and a ground, and a first clamp circuit coupled between a gate of the transistor and a drain of the transistor.

In some aspects, an apparatus includes a transformer including a first inductor, a second inductor, and a third inductor. The apparatus also includes a power amplifier coupled to the first inductor, a first antenna coupled to a first terminal of the second inductor, a second antenna coupled to a second terminal of the second inductor, a first switch coupled between the first terminal of the second inductor and a ground, a second switch coupled between the second terminal of the second inductor and the ground, and a low-noise amplifier coupled to the third inductor.

Antenna switching scheme

An RF driver circuit may include a wideband output impedance matching and gain circuit, a wideband input impedance matching and gain circuit, and a summer configured to sum the outputs of the wideband output impedance matching and gain circuit and wideband input impedance matching and gain circuit. The wideband output impedance matching and gain circuit and wideband input impedance matching and gain circuit may collectively provide the gain of the RF driver circuit. The wideband output impedance matching circuit may have a source follower configuration. The wideband input impedance matching circuit may have a common gate configuration. Controllable bias voltages may be used to maintain a constant gain and interface impedances in multiple modes of operation.

RF output driver

Various aspects described herein relate to low-loss multi-band multiplexing schemes for a wireless communications system, for example, a 5th Generation (5G) New Radio (NR) system. In an aspect, a multiplexer for multi-band wireless communications comprises at least one tuning component configured to transmit or receive at least one signal within a frequency band that is selected from a plurality of frequency bands. The multiplexer further comprises at least one combining component, communicatively coupled with the at least one tuning component, configured to transmit or receive the at least one signal within the selected frequency band. In an aspect, the at least one tuning component is integrated on a chip and the at least one combining component is not integrated on the chip.

Techniques for low-loss multi-band multiplexing

Devices and techniques are described to extract specific frequency band signals from a wide-band radio-frequency signal. A network entity may include an antenna for receiving the wide-band radio-frequency signal and may include a receiver circuit for processing the wide-band radio-frequency signal. The receiver circuit may include a transconductance amplifier and a plurality of single-band circuits. The transconductance amplifier may be configured to generate an amplified wide-band radio-frequency signal and send it to one or more of the single-band circuits. Each single-band circuit may be configured to extract a different frequency band signal from the amplified wide-band radio-frequency signal.

Multi-band radio-frequency reception

Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.

Re-timing based clock generation and residual sideband (RSB) enhancement circuit

A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

Phase continuity technique for frequency synthesis

Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.

Local oscillator buffer and mixer having adjustable size

Method and apparatus for configuring a transmitter circuit to support linear or polar mode. In the linear mode, a baseband signal is specified by adjusting the amplitudes of in-phase (I) and quadrature (Q) signals, while in the polar mode, the information signal is specified by adjusting the phase of a local oscillator (LO) signal and the amplitude of either an I or a Q signal. In an exemplary embodiment, two mixers are provided for both linear and polar mode, with a set of switches selecting the appropriate input signals provided to one of the mixers based on whether the device is operating in linear or polar mode. In an exemplary embodiment, each mixer may be implemented using a scalable architecture that efficiently adjusts mixer size based on required transmit power.

Linear and polar dual mode transmitter circuit

A receiver with a balanced I/Q transformer is described. In an exemplary design, the receiver includes an LNA that amplifies a received RF signal and provides a single-ended RF signal to the balanced I/Q transformer. The balanced I/Q transformer includes at least one primary coil and first and second secondary coils. The first secondary coil is magnetically coupled to the at least one primary coil and provides a first differential RF signal to a first mixer. The second secondary coil is magnetically coupled to the at least one primary coil and provides a second differential RF signal to a second mixer. The first and second mixers downconvert the first and second differential RF signals with I and Q LO signals, respectively, and provide differential I and Q downconverted signals. The primary and secondary coils may be fabricated on two conductive layers of an integrated circuit.

Receiver with balanced I/Q transformer

A tracking filter for attenuating out-of-band signals and adjacent channel signals in a receiver is described. In one exemplary design, an apparatus includes a tracking filter, an LNA, and a downconverter. The tracking filter includes a summer, a filter, and an upconverter. The summer subtracts a feedback signal from an input signal and provides a first signal. The LNA amplifies the first signal and provides a second signal. The downconverter frequency downconverts the second signal and provides an output signal. The filter filters (e.g., differentiates) the output signal and provides a third signal. The filter blocks a desired signal and passes out-of-band signal components. The upconverter frequency upconverts the third signal and provides a fourth signal from which the feedback signal is derived. The tracking filter has an equivalent bandpass filter response and a variable center frequency determined based on the frequency of the desired signal.

Growing community of inventors

San Diego, CA, United States of America

Ravi Sridhara