International Business Machines Corporation

Ravi Shah

Nobuhiro Asai

Andrew B Cornwall

Akira Saitoh

Rajan Raman

Rajesh Ramkrishna Bordawekar

Hayato Uenohara

Jason R Gary

Michael B Beaver

Jonathan D Costello

A method, system and computer program product for preserving event data for lazily-loaded macro components. Upon detecting an event published by a publisher, the logical channel of the detected event is identified. If one of the macro components to be lazily-loaded is a primary receiver for that logical channel (determined by performing a table-lookup of a data structure containing a listing of macro components and their associated logical channels for which they are to be the primary receivers), then the indication of the logical channel of the detected event along with the data of the published event are stored as a key/value pair in a data structure. Upon the macro component to be lazily-loaded having been loaded, the data of the published event associated with the logical channel for which the loaded macro component is a primary receiver is retrieved and transmitted to that logical channel.

Preserving event data for lazily-loaded macro components in a publish/subscribe system

A virtual machine can be extended to be aware of secondary cores and specific capabilities of the secondary cores. If a unit of platform-independent code (e.g., a function, a method, a package, a library, etc.) is more suitable to be run on a secondary core, the primary core can package the unit of platform-independent code ('code unit') and associated data according to the ISA of the secondary core. The primary core can then offload the code unit to an interpreter associated with the secondary core to execute the code unit.

Processing code units on multi-core heterogeneous processors

Provided is a method that enables an interpretive engine to execute in a non-homogeneous, multiple processor architecture. Am interpretive engine is modified to identify code native to a target processor that is executing an ISA different than the ISA of the processor executing the interpretive engine. An intermediate function is called to correlate the native code with a processor type and a target processor is identified. A context is created for the native code and the context is either transmitted to the target processor or stored in a memory location such that the target processor may retrieve the context. Once the context is transmitted, the target processor executes the task. Results are either transmitted to the originating processor or placed in memory such that the originating processor can access the result and the originating processor is signaled of the completion of the task.

Running native code across single or multi-core hybrid processor achitecture

Executing platform-independent code on multi-core heterogeneous processors

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Laveen, AZ, United States of America

Ravi Shah