Advanced Micro Devices Corporation

Cswitch Corporation

Xilinx, Inc.

Agate Logic, Inc.

Other

Achronix Semiconductor Corporation

Velogix, Inc.

Csitch Corporation

Ravi S Sunkavalli

Hare Krishna Verma

Manoj Gunwani

Narbeh Derhacobian

Elliott Delaye

Sameer S Haddad

Ravi Nagarajarao Kurlagunda

Janet S Wang

Chandra Mulpuri

Mark T Ramsbey

Michael Allen Van Buskirk

Chandrasekhar S Thyamagondlu

Rahul Nimaiyar

Hidehiko Shiraiwa

Darlene G Hamilton

Colin Stewart Bill

Ravi Prakash Gutala

Jean Y Yang

Sudip K Nag

David Michael Rogers

Wing Han Leung

John Chen

Vijay Bantval

Yider Wu

Darren S Jue

Tao Yu

Kulachet Tanpairoj

Jonathan S Su

Vei-Han Chan

Janet S Y Wang

Bo Hu

Ashok Vittal

Hanh Hoang

Conrad Kong

Akhil Krishnan

Kushagra Sharma

Vei-Han Chen

Angela Tai Hui

Tuan Duc Pham

Feng Q Pan

Richard M Fastow

Mark W Randolph

Lee Edward Cleveland

Kazuhiro Kurihara

Timothy J Thurgate

Shane Charles Hollmer

Anujan Varma

Edward V Bautista, Jr

Weng Fook Lee

Tim Thurgate

Chuan Cheng Pan

Kenneth Chan

Ellery Cochell

Patrick C McCarthy

Victor J Wu

Poching Sun

John West

A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.

Multi-host direct memory access system for integrated circuits

A direct memory access (DMA) system can include a memory configured to store a plurality of host profiles, a plurality of interfaces, wherein two or more of the plurality of interfaces correspond to different ones of a plurality of host processors, and a plurality of data engines coupled to the plurality of interfaces. The plurality of data engines are independently configurable to access different ones of the plurality of interfaces for different flows of a DMA operation based on the plurality of host profiles.

A circuit arrangement includes a memory circuit, data upload circuitry, data formatting circuitry, and a systolic array (SA). The data upload circuitry inputs a multi-dimensional data set and stores the multi-dimensional data set in the memory circuit. The data formatting circuitry reads subsets of the multi-dimensional data set from the memory circuit. The data formatting circuitry arranges data elements of the subsets into data streams, and outputs data elements in the data streams in parallel. The SA includes rows and columns of multiply-and-accumulate (MAC) circuits. The SA inputs data elements of the data streams to columns of MAC circuits in parallel, inputs filter values to rows of MAC circuits in parallel, and computes an output feature map from the data streams and the filter values.

Data formatter for convolution

A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.

Dynamically reconfigurable networking using a programmable integrated circuit

Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.

Customizable multi queue DMA interface

An integrated circuit (IC) includes a first kernel circuit implemented in programmable circuitry, a second kernel circuit implemented in programmable circuitry, and a stream traffic manager circuit coupled to the first kernel circuit and the second kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the first kernel circuit and the second kernel circuit.

Streaming platform architecture for inter-kernel circuit communication for an integrated circuit

A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit. The encryption circuit encrypts the plaintext input packet based on the first cryptographic parameters, and the decryption circuit decrypts the ciphertext input packet based on the second cryptographic parameters.

Cryptographic system

Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.

Hierarchical global clock tree

A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

System and method of signal processing engines with programmable logic fabric

A programmable system is disclosed having multiple configurable floating point units ('FPU') that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

Programmable logic systems and methods employing configurable floating point units

Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. One or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Reset signal distribution

Methods, circuits and systems for balanced distribution of source-synchronous clock signals are described. Multiple data sets together with one or more clock signals associated with the multiple data sets may be received at a number of interface devices. The multiple data sets may be captured in a number of data buffers. The clock signals may be programmably distributed to a group of the multiple data buffers that retain the one or more data sets, using a balanced clock network. Additional methods, circuits, and systems are disclosed.

Source-synchronous clocking

Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Growing community of inventors

Santa Clara, CA, United States of America

Ravi S Sunkavalli