Intel Corporation

Ravi S Rao

Byron R Gillespie

Elliot D Garbus

Joseph Murray

Terence Sych

Dinesh Ranganathan

Real-time performance monitoring facility in an integrated circuit (IC) data processor for monitoring events related to different bus activity. The monitoring facility is accessible via a bus connection the IC. Events include device acquisition and ownership time, and the number of requests and grants on a given bus. The events are counted as occurrences and durations by a number of event counters integrated in the IC. The IC can notify software when the counters overflow. The IC may feature multiple clock domains, including, for instance, multiple bus interfaces operating at different clock frequencies, in which events from different clock domains may be tracked by the same counter. In one embodiment, the performance monitoring facility is integrated into an I/O processor (IOP) die that complies with the popular intelligent I/O (I O) and Peripheral Components Interconnect (PCI) specifications.

Integrated real-time performance monitoring facility

An application accelerator (AA) unit that in one embodiment is part of an I/O processor (IOP) integrated circuit. The AAU includes logic circuitry for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). A boolean unit performs operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is written to the redundant disk array. The AAU is associated with a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating RAID storage applications as well as local memory DMA-type transfers, using the descriptor construct.

Boolean and movement accelerator

A method and apparatus for monitoring an event is disclosed. In one embodiment, a ratio counter is provided which includes a first counter having a first count and a second counter having a second count. The method increments the first count of the first counter on an occurrence of an event by a first device and shifts the ratio counter to the right by a predetermined number of bits when the first count reaches a maximum count. The method further takes a ratio between the first count and the second count where the ratio indicates the relative occurrence of the event by the first device and a second device. In another embodiment, the method decrements the second count of the second counter when the first count reaches a maximum count. In yet another embodiment, the method decrements the first count of the first counter and the second count of the second counter when the first count reaches a maximum count.

Method and apparatus for providing scaled ratio counters to obtain agent

An application accelerator unit (AAU) that is integrated as part of a data processor, such as an I/O processor (IOP) integrated circuit. In one embodiment, the AAU includes logic for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). The AAU performs boolean operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is then written to the redundant disk array. Additionally, the AAU may feature adder logic configured to perform an addition such as a network header checksum calculation on each data packet. The AAU includes a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating storage and networking applications as well as for local memory DMA-type transfers, using the chain descriptor construct.

Growing community of inventors

Phoenix, AZ, United States of America

Ravi S Rao