Neomagic Corporation

Ravi Ranganathan

Deepraj S Puar

Clement K Leung

A graphics controller system which has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals, all in the form of a CMOS integrated circuit. The video memory is integrated on the same integrated circuit as the graphics controller; no package pins are required for the memory interface. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Graphics controller integrated circuit without memory interface

A CMOS integrated circuit which has a graphics controller system that has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with package pin connections.

A graphics controller system which has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals, all in the form of a CMOS integrated circuit. The video memory is integrated on the same integrated circuit as the graphics controller; no package pins are required for the memory interface. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection

A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

A video sub-system features reduced power consumption by integrating a video memory onto the same chip as the video memory controller. The video memory is preferably a small DRAM sufficiently large to store all pixel data for lower resolutions, but insufficient for higher resolutions. At higher resolutions, an external DRAM supplements the internal DRAM. The amount of external DRAM needed depends upon the resolution to be supported. The internal DRAM has a wide data bus and thus high bandwidth, since no external I/O pins are needed. The external DRAM is narrow to minimize pincount and power consumption. Since the external DRAM is slower and lower in bandwidth, pixel data from both internal and external DRAMs are interleaved together for each horizontal scan line. Thus the lower bandwidth of the external DRAM is masked by the high bandwidth of the wide internal DRAM. Either the internal or the external DRAM, or both, are automatically tested with a pseudo-random number generator that writes pseudo-random numbers to the DRAM while simultaneously supplying pixel data to the graphics data path for display. A checksum of the pixel data output from the graphics data path is generated for the first screen of pixels or frame, while on the second frame the pseudo-random number generator is disabled and the DRAM supplies the same pixel data that was written to it by the pseudo-random number generator during the first frame. The checksums for the first and second frames should match if the DRAM is free of faults.

Testable interleaved dual-DRAM architecture for a video memory

Graphics controller integrated circuit without memory interface pins and

A graphics controller chip has an integrated graphics memory. A wide data interface is provided to a RAM array storing graphics pixel data in the graphics memory. The wide data interface provides 256 bits of data during normal writes, but in a block-write mode the wide data interface is split into two sections. One section contains 128 bits of data, while a second section contains 128 mask bits. The data is replicated to eight half-width columns in the RAM array, while the mask bits disable writing some of the data to the RAM. Separate byte-mask bits can be provided for disabling bytes during normal mode writes, but these byte-mask bits cause multiple copies of the data to be disabled. Thus the mask bits in the second section are more useful as they can disable any individual byte in any of the eight columns. A block write of 64 2-byte pixels can be performed in a single step, as no color-data register and no mask register is needed. The 128 bits of data provide an 8-pixel data pattern which is copied to eight columns. The 8-pixel data pattern provides a complex 8-color pattern for background fills behind foreground graphics data.

Multiplexed wide interface to SGRAM on a graphics controller for

A graphics controller has a standard RGB graphics pixel path from a graphics memory. A second path from the graphics memory transfers movie-overlay pixels in YUV format. Two pixel muxes are used. Each pixel mux selects either RGB graphics pixels or YUV movie pixels converted to the RGB color space. A first pixel mux loads either the graphics or the movie pixels to a path to the external CRT. A second pixel mux loads either the graphics or the movie pixels to an LCD path leading to a flat-panel LCD display. The pixel muxes can act in unison to display the same image on both the external CRT and the local LCD panel, and the movie pixels may be overlaid as a small window over the graphics data. The pixel muxes can also act separately so that different images are displayed on the external CRT and the local LCD panel. One pixel mux selects the RGB pixels while the other pixel mux selects the converted YUV pixels. The RGB pixels can be displayed on the LCD panel as graphics data such as speaker's notes, while the YUV pixels can be displayed as a full-screen movie window on the external CRT to an audience. Thus a single graphics controller in a portable PC can drive two different images--one for the audience on the external CRT and a second for the speaker on the portable PC's LCD panel display.

Multiplexed yuv-movie pixel path for driving dual displays

A graphics controller overlays a movie window over the graphics pixel data. Movie pixels are from a movie source and are muxed into the pixel path by a pixel mux near the end of the graphics pipeline. A comparison of the current pixel count to the pixel address of the start and ending boundaries of the movie window controls the pixel mux, which selects either graphics pixels or movie pixels for display to a screen. Since the graphics controller is pipelined, the pixel compare near the end of the pipeline does not restart the graphics pipeline early enough for it to pre-process the graphics pixels. The graphics pipeline does not stop during the movie window but instead performs dummy fetches from the graphics memory to a CRT FIFO in the graphics pipeline. Dummy fetches are fetches of graphics pixels that are not displayed. Since these fetches contain non-displayed pixels, they are not needed except to keep the fetch count counting even during the movie window. Other requests are given priority during dummy fetches. Thus fetches to fill the CRT FIFO with pixels underneath the movie overlay which are not displayed are transparently blocked by activating dummy fetches, allowing other requestors to have full access to the graphics memory. Dummy fetches are activated by a compare of the fetch counts to the width of the graphics and movie portions of the screen, expressed in memory fetches rather than in pixels. A comparison of the total fetches in a horizontal line to the current fetch count prevents fetching un-displayed pixels past the end of the line.

Transparent blocking of CRT refresh fetches during video overlay using

A video sub-system features reduced power consumption by periodically disabling the video controller clocks used for transferring pixel data to a screen. The video clocks are pulsed only when pixel data is being transferred to the screen, during the time that a horizontal line of pixels is being scanned on the screen. The video clocks are not pulsed during the horizontal and vertical blanking periods, when the electron beam in a cathode-ray-tube is being re-traced. The video clocks are also not pulsed during a recovery period for a flat-panel screen. A video memory contains pixel information for the entire screen and is controlled by a memory controller. The memory controller uses a memory clock to transfer all or part of a horizontal line of pixels to a video buffer. The pixel data is then read out of the video buffer to the screen in a serial fashion, synchronized to the video clock. Host data may be written to a host buffer using a bus clock from the host, and then written to the video memory using the memory clock. The memory clock is only pulsed when data is transferred to or from the video memory, or during memory refresh. The memory clock is not pulsed when the video memory is idle. Power consumption is reduced by enabling or pulsing the memory clock and the internal bus clock only when a transfer request is received, pending, or in progress.

Clock management for power reduction in a video display sub-system

A controller chip has dynamic logic which is driven by a suspendable clock. Power is reduced in a standby mode when the clock to the dynamic logic is stopped. However, power is still applied to the dynamic logic in standby mode so that the dynamic logic can be quickly resumed without the delay of re-charging the power-supply capacitances in the dynamic logic. Stopping the clock to dynamic logic can eventually cause loss of data. A more severe problem than data loss is power consumption. When the clock is stopped to dynamic logic, the isolated nodes leak and eventually their voltages change. When their voltages change by more than a transistor threshold voltage then both the p-channel and n-channel transistors in dynamic logic cells can turn on, forming a direct current paths between power and ground. Thus power consumption can increase dramatically in suspend mode. The isolated dynamic nodes of the dynamic logic are instead recharged periodically during suspend mode. A timer triggers generation of intermittent clock pulses which are applied to the clock to the dynamic logic, recharging the isolated nodes. When data loss can be tolerated, the intermittent pulses ensure that power consumption does not jump due to the voltage changes on the isolated dynamic nodes.

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Cupertino, CA, United States of America

Ravi Ranganathan