Intel Corporation

Wisconsin Alumni Research Foundation

Intel Corparation

Ravi Rajwar

Konrad K Lai

Martin Guy Dixon

Matthew C Merten

Haitham H Akkary

Bret L Toll

Srikanth T Srinivasan

Peter Lachner

Laura A Knauth

James R Goodman

Robert S Chappell

Rajesh S Parthasarathy

Vijaykumar Balaram Kadgi

Ali-Reza Adl-Tabatabai

Stephan Jourdan

Bratin Saha

Mingqiu Sun

Andrew Thomas Forsyth

Lily Pao Looi

Alexandre J Farcy

Suresh Srinivas

Peggy J Irelan

Ilhyun Kim

Zhongying Zhang

Uma Srinivasan

Stephen H Dohrmann

Prakash Math

Jason Bessette

Robert A Mayer

David M Durham

Ravi L Sahita

Mark Jay Charney

Vedvyas Shanbhogue

Barry E Huntley

Edward Thomas Grochowski

Raanan Sade

Michael Lemay

Matthew Mattina

Eric A Sprangle

Maurice P Herlihy

Paul Caprioli

Beeman C Strong

Ofer Levy

Joshua B Fryman

Alain Kagi

Richard Lewis Hudson

Ramacharan Sundararaman

Roger Espasa

Tong Li

Ady Tal

James Hadley

Omar M Shaikh

Muawya M Al-Otoom

Alex Gerber

Roman Dementiev

Justin M Deinlein

Pritpal S Ahuja

Yury N Ilin

Christine E Wang

John Cruz Mejia

Toni Juan

Thilo Schmitt

Thomas F Toll

Thomas Toll

Joseph A McMahon

Amit Gandhi

David Lim

Adl-Tabatabai Ali-Reza

An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution

Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution

In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

Tracking mode of a processing device in instruction tracing systems

Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Instruction and logic to test transactional execution status

Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.

Throttling integrated link

Suspendable load address tracking inside transactions is disclosed. An example processing device of implementations of the disclosure includes a transactional memory (TM) read set tracking component circuitry to identify a suspend read tracking instruction within a transaction executed by the processing device, mark load instructions occurring in the transaction subsequent to the identified suspend read tracking instruction with a suspend attribute, wherein the addresses corresponding to the marked load instructions are excluded from a read set maintained for the transaction, identify a resume read tracking instruction within the transaction, and stop marking the load instructions occurring subsequent to the identified resume read tracking instruction with the suspend attribute.

Suspendable load address tracking inside transactions

In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Last branch record indicators for transactional memory

A method and apparatus for post-retire transaction access tracking is herein described. Load and store buffers are capable of storing senior entries. In the load buffer a first access is scheduled based on a load buffer entry. Tracking information associated with the load is stored in a filter field in the load buffer entry. Upon retirement, the load buffer entry is marked as a senior load entry. A scheduler schedules a post-retire access to update transaction tracking information, if the filter field does not represent that the tracking information has already been updated during a pendency of the transaction. Before evicting a line in a cache, the load buffer is snooped to ensure no load accessed the line to be evicted.

Post-retire scheme for tracking tentative accesses during transactional execution

Generally, this disclosure provides systems, devices, methods and computer readable media for protecting confidential data with transactional processing in execute-only memory. The system may include a memory module configured to store an execute-only code page. The system may also include a transaction processor configured to enforce a transaction region associated with at least a portion of the code page. The system may further include a processor configured to execute a load instruction fetched from the code page, the load instruction configured to load at least a portion of the confidential data from an immediate operand of the load instruction if a transaction mode of the transaction region is enabled.

Protecting confidential data with transactional processing in execute-only memory

A processor, system, and method are described for continued retirement of operations during a commit of a speculative region of program code. For example, one embodiment of a method comprises the operations of identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and retiring one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete.

Method and apparatus for continued retirement during commit of a speculative region of code

Growing community of inventors

Portland, OR, United States of America

Ravi Rajwar