Qualcomm Incorporated

Ravi Pramod Kumar Vedula

George P Imthurn

Sinan Goktepeli

Hyunchul Jung

Qingqing Liang

Abhijeet Paul

Stephen Alan Fanelli

Sivakumar Kumarasamy

Christopher Nelles Brindle

Periannan Chidambaram

Anton Arriagada

Vikram Sekar

Mishel Matloubian

Jarred Moore

Farid Azzazy

Yufei Wu

A complementary metal oxide semiconductor (CMOS) integrated humidity sensor with built-in heater is disclosed. In an aspect, a capacitive humidity sensor comprises a substrate and a plurality of unit humidity sensors disposed above the substrate. Each unit humidity sensor comprises a resistive heating structure disposed above the substrate, a plurality of capacitive humidity sensors disposed above the resistive heating structure and set apart from each other in a vertical direction, and a top surface at least a portion of which is water-permeable. Each capacitive humidity sensor comprises a pair of interdigitated vertical metal plates extending in a first direction, set apart from each other in a second direction orthogonal to the first direction, and separated from each other by a moisture-sensitive dielectric disposed between the pair of interdigitated vertical metal plates. At least one capacitive humidity sensor uses a different moisture-sensitive dielectric than another capacitive humidity sensor.

CMOS integrated humidity sensor with built-in heater

Disclosed is a transistor of a device that has an asymmetric resistance or an asymmetric capacitive coupling or both. When used in a cascode configuration in an amplifier, low current performance of the amplifier is improved. Asymmetric resistance may be enabled through differentially doping source and drain structures of the transistor and/or through differentially manipulating geometries the source and drain structures. Asymmetric capacitive coupling may be enabled through providing dielectrics and differentially locating the dielectrics above a gate of the transistor. Further, a body of the transistor may be biased.

Enhanced MOSFET with superior RF performance

A dual-sided MOS IC includes an isolation layer and a MOS transistor. The isolation layer separates the MOS IC into a MOS IC frontside and a MOS IC backside. The MOS transistor is on both the MOS IC frontside and the MOS IC backside. The MOS transistor includes MOS gates, a first source connection in a first subsection of the MOS IC frontside, and a second source connection in a second subsection of the MOS IC backside. The first and second source connections are electrically coupled together through a first front-to-backside connection extending through the isolation layer. The MOS transistor further includes a first drain connection in the first subsection of the MOS IC backside, and a second drain connection in the second subsection of the MOS IC frontside. The first and second drain connections are electrically coupled together through a second front-to-backside connection extending through the isolation layer.

Symmetric dual-sided MOS IC

A radio frequency integrated circuit (RFIC) is described. The RFIC includes a switch field effect transistor (FET). The switch FET includes a source region, a drain region, a body region, and a gate region. The RFIC also includes a dynamic bias control circuit. The dynamic bias control circuit includes at least one transistor coupled between the body region and the gate region of the switch FET.

Dynamic body biasing for radio frequency (RF) switch

A radio frequency (RF) device is described. The RF device includes a switch field effect transistor (FET), having a source region, a drain region, a body region, and a gate region. The RF device also includes a dynamic bias control circuit. The dynamic bias control circuit includes a first transistor coupled to the gate region of the switch FET by a gate resistor. The dynamic bias control circuit also includes a second transistor coupled to the first transistor and coupled to the body region of the switch FET by a body resistor. The dynamic bias control circuit further includes a capacitor coupled to the body region of the switch FET by the body resistor, and the gate region of the switch FET, by the gate resistor.

A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

Series shunt biasing method to reduce parasitic loss in a radio frequency switch

An optically powered switch. An example optically powered switch generally includes a light source configured to output an optical signal. The example optically powered switch generally includes a photodiode configured to convert the optical signal to an electrical signal. The example optically powered switch generally includes a bias and control circuit configured to power at least one radio frequency (RF) switch using the electrical signal.

Optically powered switch and method for operating an optically powered switch

A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.

High voltage (HV) metal oxide semiconductor field effect transistor (MOSFET) in semiconductor on insulator (SOI) technology

A dual sided contact switch has a first independent drain/source region of a multi-gate active device. The dual sided contact switch also has a first shared drain/source region of the multi-gate active device. The dual sided contact switch has a second independent drain/source region of the multi-gate active device, adjacent to the first shared drain/source region. The dual sided contact switch also has a second shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the first shared drain/source region, and also between the second independent drain/source region and the second shared drain/source region.

Capacitance balance in dual sided contact switch

A radio frequency integrated circuit (RFIC) includes multi-finger transistors including discrete diffusion regions and interconnected within a reconfigured form factor as a single switch transistor. The RFIC also includes a source bus having a first plurality of source fingers coupled to each source region of the multi-finger transistors and a second plurality of source fingers orthogonally coupled to the first plurality of source fingers. The second plurality of source fingers couple the discrete diffusion regions in parallel. The RFIC also includes a drain bus having a first plurality of drain fingers coupled to each drain region of the multi-finger transistors and a second plurality of drain fingers orthogonally coupled to the first plurality of drain fingers. The second plurality of drain fingers electrically couple the discrete diffusion regions in parallel. The RFIC further includes a plurality of interconnected body contacts to bias a body of each of the multi-finger transistors.

Transistor layout for improved harmonic performance

An integrated circuit is described. The integrated circuit includes a metal oxide semiconductor field effect transistor (MOSFET). The MOSFET is on a first surface of an insulator layer of the integrated circuit. The MOSFET including a source region, a drain region, and a front gate. The MOSFET also includes an extended drain region between the drain region and a well proximate the front gate. The integrated circuit also includes back gates on a second surface opposite the first surface of the insulator layer. The back gates are overlapped by the extended drain region.

A semiconductor device includes a channel structure that includes a first oxide layer, a second oxide layer, and a channel region between the first oxide layer and the second oxide layer. The semiconductor device includes a first gate structure proximate to at least three sides of the channel structure. The semiconductor device includes a second gate structure proximate to at least a fourth side of the channel structure.

Wrap-around gate structures and methods of forming wrap-around gate structures

A radio frequency (RF) integrated circuit (RFIC) switch multi-finger transistor includes a first dual gate transistor having a first gate with a first gate length on a first side of a substrate, and a second gate with a second gate length on a second side of the substrate. The RFIC also includes a second dual gate transistor having a third gate with a third gate length on the first side of the substrate, and a fourth gate with a fourth gate length on the second side of the substrate. The second gate length is different than the fourth gate length, and the second dual gate transistor is coupled in series with the first dual gate transistor in the RFIC switch multi-finger transistor.

Capacitive tuning using backside gate

A radio frequency integrated circuit (RFIC) is described. The RFIC includes a switch field effect transistor (FET), including a source region, a drain region, a body region, and a gate. The RFIC also includes a body bypass resistor coupled between the gate and the body region. The RFIC further includes a gate isolation resistor coupled between the gate and the body region. The RFIC also includes a diode coupled between the body bypass resistor and the gate isolation resistor.

Growing community of inventors

San Diego, CA, United States of America

Ravi Pramod Kumar Vedula